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公开(公告)号：US07277449B2
公开(公告)日：2007-10-02
申请号：US10207298
申请日：2002-07-29
IPC分类号： H04L12/28
CPC分类号： H04L49/30 , H04L49/101 , H04L49/102 , H04L49/109 , H04L49/254
摘要： An OCN for integrated processing elements including a network with multiple ports and multiple port interfaces. The ports and the port interfaces conform to a consistent port protocol. Each port interface converts information between bus transactions of a corresponding processing element and network packets and exchanges network packets with other port interfaces. Each port includes an arbitration interface and a data interface and the network includes an interconnect and an arbiter. The interconnect includes selectable data paths between the ports for packet datum transfer. A port source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. A port destination interface receives packet datums via available input buffers. Each transaction request includes a transaction size and a destination port address. The arbiter receives transaction requests, arbitrates among transaction requests, provides acknowledgements and controls the interconnect to select data paths between sources and destinations.
摘要翻译： 用于集成处理元件的OCN，包括具有多个端口和多个端口接口的网络。 端口和端口接口符合一致的端口协议。 每个端口接口在对应处理单元的总线事务和网络数据包之间转换信息，并与其他端口接口交换网络数据包。 每个端口包括仲裁接口和数据接口，并且网络包括互连和仲裁器。 互连包括用于分组数据传输的端口之间的可选数据路径。 端口源接口在接收到确认后提交事务请求并提供数据包基准。 端口目的地接口通过可用的输入缓冲区接收数据包基准。 每个事务请求都包含事务大小和目标端口地址。 仲裁器接收事务请求，在事务请求之间进行仲裁，提供确认并控制互连以选择源和目的地之间的数据路径。
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公开(公告)号：US07139860B2
公开(公告)日：2006-11-21
申请号：US10207588
申请日：2002-07-29
CPC分类号： G06F15/78
摘要： An OCN with independent logical and physical layers for enabling communication among integrated processing elements, including ports, bus gaskets and a physical layer interface. Each bus gasket includes a processor element interface and a port interface. Each processor element interface of at least two bus gaskets operates according to a first logical layer protocol. Each port interface operates according to a consistent port interface protocol by sending transaction requests and receiving acknowledgements and by sending and receiving packet datums via the corresponding port. The physical layer interface transfers packets between the ports and includes an arbiter and an interconnect coupled to each port. Additional bus gaskets may be added that operate according to a second logical layer protocol which may or may not be compatible with the first. Any bus gasket may be added that is configured to communicate using multiple logical layer protocols.
摘要翻译： 具有独立逻辑和物理层的OCN，用于实现集成处理元件之间的通信，包括端口，总线衬垫和物理层接口。 每个总线衬垫包括处理器元件接口和端口接口。 至少两个总线衬垫的每个处理器元件接口根据第一逻辑层协议进行操作。 每个端口接口通过发送事务请求和接收确认以及通过相应端口发送和接收数据包基准，根据一致的端口接口协议进行操作。 物理层接口在端口之间传送数据包，并包括耦合到每个端口的仲裁器和互连。 可以添加额外的总线衬垫，其可以根据第二逻辑层协议操作，第二逻辑层协议可以或可以不与第一逻辑层协议兼容。 可以添加配置为使用多个逻辑层协议进行通信的任何总线衬垫。
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3.发明授权On chip network that maximizes interconnect utilization between processing elements 有权片上网络，可最大限度地提高处理元件之间的互连利用率公开(公告)号：US07200137B2
公开(公告)日：2007-04-03
申请号：US10207459
申请日：2002-07-29
IPC分类号： H04L12/28
CPC分类号： H04L49/254 , H04L49/3018
摘要： A network that maximizes interconnect utilization between integrated processing elements, including ports, an interconnect, port interfaces, and an arbiter. Each port includes arbitration and data interfaces. The interconnect includes selectable data paths between the ports for packet datum transfer. Each port interface includes processing, source and destination interfaces. The source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. The destination interface receives packet datums via a number of available input buffers. Each transaction request includes a transaction size, a packet priority, and a destination port address. The arbiter includes a request queue and a buffer counter for each port and a datum counter for each acknowledged transaction. The arbiter arbitrates among transaction requests based on a selected arbitration scheme, destination buffer availability, data path availability, and priority, and uses the packet datum counters, arbitration latency and data path latency to minimize dead cycles in the interconnect.
摘要翻译： 最大化集成处理元素之间的互连利用率的网络，包括端口，互连，端口接口和仲裁器。 每个端口包括仲裁和数据接口。 互连包括用于分组数据传输的端口之间的可选数据路径。 每个端口接口包括处理，源和目标接口。 源接口在接收到确认后提交事务请求并提供数据包基准。 目的地接口通过多个可用的输入缓冲区接收数据包基准。 每个事务请求包括事务大小，分组优先级和目标端口地址。 仲裁器包括每个端口的请求队列和缓冲区计数器以及每个确认的事务的基准计数器。 仲裁器根据选定的仲裁方案，目的缓冲区可用性，数据路径可用性和优先级在事务请求之间进行仲裁，并使用分组数据计数器，仲裁延迟和数据路径等待时间来最小化互连中的死循环。
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公开(公告)号：US07051150B2
公开(公告)日：2006-05-23
申请号：US10207600
申请日：2002-07-29
IPC分类号： G06F13/00
CPC分类号： G06F15/78
摘要： A scalable network for supporting an application using processing elements including ports, an interconnect, port interfaces, and an arbiter. Each port conforms to a consistent port interface protocol regardless of number of ports, frequency of operation, maximum datum width or data path concurrency. The interconnect has a scalable maximum datum width and a scalable data path concurrency, and includes selectable data paths between any two ports to enable transfer of datums between the ports. Each port interface formulates packets for transmission and receives packets via the corresponding port and the interconnect, where each packet includes one or more datums. The arbiter controls packet transfer via the interconnect between source and destination ports. The interconnect has a scalable data path concurrency. Pipeline stages may be added to support a selected clock frequency. The OCN may be a component library including bus gasket, interconnect and arbiter components.
摘要翻译： 可扩展网络，用于使用包括端口，互连，端口接口和仲裁器的处理元件支持应用程序。 每个端口符合一致的端口接口协议，无论端口数量，操作频率，最大基准宽度或数据路径并发。 互连具有可扩展的最大基准宽度和可伸缩的数据路径并发性，并且包括任何两个端口之间的可选数据路径，以实现端口之间的基准传输。 每个端口接口配置数据包进行传输，并通过相应的端口和互连接收数据包，每个数据包包含一个或多个数据。 仲裁器通过源端口和目的端口之间的互连来控制数据包传输。 互连具有可扩展的数据路径并发性。 可以添加管道级以支持选定的时钟频率。 OCN可以是包括总线衬垫，互连和仲裁器组件的组件库。
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公开(公告)号：US06996651B2
公开(公告)日：2006-02-07
申请号：US10207609
申请日：2002-07-29
IPC分类号： G06F13/00
CPC分类号： G06F13/36
摘要： A network with memory device address decoding that enables communication among integrated processing elements, including a network, a processing element and a bus gasket. The network transfers packets between multiple ports, where each port conforms to a consistent port interface protocol. The processing element includes a bus and a memory device programmed with the address of each port, so that a transaction on the bus indicating another port is decoded by the memory device. The bus gasket includes a bus interface that generates packets and a port interface that sends and receives the packets according to the consistent port interface protocol and that uses the decoded address as a destination port address. The memory device may be implemented in any desired manner, such as a memory management unit (MMU) or a direct memory access (DMA) device.
摘要翻译： 具有存储器件地址解码的网络，其能够实现集成处理元件之间的通信，包括网络，处理元件和总线衬垫。 网络在多个端口之间传输数据包，其中每个端口都符合一致的端口接口协议。 处理元件包括总线和用每个端口的地址编程的存储器件，使得指示另一端口的总线上的事务被存储器件解码。 总线衬垫包括一个生成数据包的总线接口和一个根据一致的端口接口协议发送和接收数据包并使用解码的地址作为目标端口地址的端口接口。 存储器设备可以以任何期望的方式来实现，诸如存储器管理单元（MMU）或直接存储器存取（DMA）设备。
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6.发明授权
公开(公告)号：US5336940A
公开(公告)日：1994-08-09
申请号：US926981
申请日：1992-08-07
申请人： Peter H. Sorrells , Ned D. Garinger
发明人： Peter H. Sorrells , Ned D. Garinger
IPC分类号： H03K5/00 , H03K5/13 , H03K19/003 , H03L7/081 , H03K5/24
CPC分类号： H03K5/13 , H03K19/00323 , H03L7/0812 , H03K2005/00097
摘要： An output pad for an integrated circuit includes circuitry to fix the output delay to a constant value even when changes occur in power supply voltage, manufacturing process and temperature. This output pad has a closed-loop feedback circuit which controls the delay of the output signal through an Adjustable Output Driver. A Fixed Delay Element provides a reference delay that does not change with induced variations. The loop adjusts the delay of the Adjustable Output Driver until the edge of the signal delayed by the Adjustable Output Driver is coincident with the edge of the signal delayed by the Fixed Delay Element within a defined tolerance. In a second embodiment the output pad has a Variable Delay Element with programmable delay values that remain constant over induced variations. In a third embodiment the Fixed Delay Element is deleted, and the delayed signal through the Adjustable Output Driver is compared to and therefore synchronized with a Reference Signal, which may be provided on-chip or from a source external to the chip.
摘要翻译： 用于集成电路的输出焊盘包括即使当电源电压，制造工艺和温度发生变化时也将输出延迟固定为恒定值的电路。 该输出焊盘具有闭环反馈电路，通过可调输出驱动器控制输出信号的延迟。 固定延迟元件提供不随诱导变化而改变的参考延迟。 该循环调节可调输出驱动器的延迟，直到由可调输出驱动器延迟的信号的边沿与定义的公差内由固定延迟元件延迟的信号的边沿重合。 在第二实施例中，输出焊盘具有可变延迟元件，可变延迟元件具有在诱导变化上保持恒定的可编程延迟值。 在第三实施例中，固定延迟元件被删除，并且通过可调输出驱动器的延迟信号与参考信号进行比较并因此与参考信号同步，该参考信号可以在芯片上或芯片外部提供。
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7.发明授权Compensated digital delay semiconductor device with selectable output taps and method therefor 失效具有可选输出抽头的补偿数字延迟半导体器件及其方法
公开(公告)号：US5281874A
公开(公告)日：1994-01-25
申请号：US836078
申请日：1992-02-14
申请人： Peter H. Sorrells , Ned D. Garinger
发明人： Peter H. Sorrells , Ned D. Garinger
CPC分类号： H03L7/0805 , H03K19/00323 , H03K5/135 , H03L7/0814 , H03K2005/00104
摘要： A compensated digital delay semiconductor device is disclosed which uses two identical chains of delay elements. The first chain is the Reference Chain, which is driven by a crystal-controlled digital clock input. The second chain is the Input Signal Delay Chain, which is the delay path for the signal of interest. These two chains are located in physical proximity on the semiconductor die so that variations in the manufacturing process, temperature and power supply affect each chain the same. Circuitry monitors the delay performance of the Reference Chain, and dynamically changes the output tap of the Input Signal Delay Chain when a change in performance is detected on the Reference Chain, thereby compensating the delay of the device. This approach provides precise delays which are constant.
摘要翻译： 公开了使用两个相同的延迟元件链的补偿数字延迟半导体器件。 第一条链是参考链，它由晶体控制的数字时钟输入驱动。 第二链是输入信号延迟链，它是感兴趣信号的延迟路径。 这两条链位于半导体管芯上物理上靠近，使得制造过程，温度和电源的变化对每个链条产生影响。 电路监视参考链的延迟性能，并且当在参考链上检测到性能变化时，动态地改变输入信号延迟链的输出抽头，从而补偿器件的延迟。 这种方法提供了不变的精确延迟。
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8.发明授权Circuit and method for converting interrupt signals from level trigger mode to edge trigger mode 失效用于将中断信号从电平触发模式转换为边沿触发模式的电路和方法
公开(公告)号：US6145047A
公开(公告)日：2000-11-07
申请号：US245950
申请日：1994-05-19
申请人： Ned D. Garinger , Tein-Yow Yu
发明人： Ned D. Garinger , Tein-Yow Yu
CPC分类号： G06F13/24
摘要： Level trigger mode interrupts are converted to edge trigger mode interrupts in a computer system. A circuit detects the occurrence of a level trigger mode interrupt request, and asserts an edge trigger mode interrupt request output. The edge trigger mode interrupt request remains asserted until an End of Interrupt input is asserted, indicating that the CPU has completed servicing the prior interrupt. The edge trigger mode interrupt request is then deasserted.
摘要翻译： 电平触发模式中断在计算机系统中转换为边沿触发模式中断。 电路检测到电平触发模式中断请求的发生，并且断言边沿触发模式中断请求输出。 边沿触发模式中断请求保持置位，直到中断输入结束为止，表明CPU已经完成对先前中断的服务。 然后边沿触发模式中断请求被置为无效。
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9.发明授权
公开(公告)号：US5365130A
公开(公告)日：1994-11-15
申请号：US926979
申请日：1992-08-07
IPC分类号： H03K5/13 , H03K19/003 , H03K5/26
CPC分类号： H03K5/131 , H03K19/00323
摘要： An output pad for an integrated circuit includes circuitry to align the output with an on-chip clock signal, and to compensate the output such that it remains coincident with the on-chip clock signal even when changes occur in power supply voltage, manufacturing process and temperature. This output pad has a closed-loop feedback circuit which controls the delay of the output signal through a variable delay element. The loop adjust the delay until the clock edge of the on-chip clock signal is coincident with the output signal within a defined tolerance. The output pad self-compensates with every clock cycle, which is many times faster than any induced variation.
摘要翻译： 用于集成电路的输出焊盘包括使输出与片上时钟信号对准的电路，并且即使当电源电压，制造过程和/或电源电压发生变化时，也可补偿输出，使其保持与片上时钟信号一致 温度。 该输出焊盘具有闭环反馈电路，其通过可变延迟元件控制输出信号的延迟。 该环路调整延迟，直到片上时钟信号的时钟边沿与所定义的公差内的输出信号一致。 每个时钟周期，输出垫自补偿，这比任何诱导的变化快许多倍。
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公开(公告)号：US5136180A
公开(公告)日：1992-08-04
申请号：US655018
申请日：1991-02-12
申请人： Kenneth P. Caviasca , Tein-Yow Yu , Ned D. Garinger , Pratiksh Parikh , W. Henry Potts , James B. Nolan
发明人： Kenneth P. Caviasca , Tein-Yow Yu , Ned D. Garinger , Pratiksh Parikh , W. Henry Potts , James B. Nolan
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： A circuit generates a system clock signal. On a first input of the circuit a first oscillating signal is placed. On a second input, a second oscillating signal may be placed. Clock sense logic is connected to the second input. The clock sense logic detects whether the second oscillation signal is present on the second input. When the second oscillating signal is not present on the second input, the first oscillating signal is selected to be used to generate the system clock. When the second oscillating signal is present on the second input, the second oscillating signal is selected to be used to generate the system clock. The selected oscillating signal is divided to produce the system clock signal. A first frequency divider divides the selected oscillating signal by a first amount. In parallel, a second frequency divider divides the selected oscillating signal by a second amount. A selector, for example, a multiplexor, selects output from either the first frequency divider or the second frequency divider as the system clock signal. When the first oscillating signal is being used to generate the system clock, the second input may be used to control the selection of frequency dividers.
摘要翻译： 电路产生系统时钟信号。 在电路的第一输入端放置第一振荡信号。 在第二输入端，可以放置第二振荡信号。 时钟检测逻辑连接到第二个输入。 时钟感测逻辑检测第二振荡信号是否存在于第二输入端。 当第二输入端不存在第二振荡信号时，选择第一振荡信号来产生系统时钟。 当第二振荡信号存在于第二输入端时，第二振荡信号被选择用于产生系统时钟。 所选择的振荡信号被分频以产生系统时钟信号。 第一分频器将选择的振荡信号除以第一量。 并行地，第二分频器将所选择的振荡信号除以第二量。 选择器，例如，多路复用器，选择来自第一分频器或第二分频器的输出作为系统时钟信号。 当第一个振荡信号用于产生系统时钟时，第二个输入可用于控制分频器的选择。
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