- 专利标题: Pseudo fail bit map generation for RAMS during component test and burn-in in a manufacturing environment
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申请号: US09931125申请日: 2001-08-16
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公开(公告)号: US07051253B2公开(公告)日: 2006-05-23
- 发明人: Randall Rooney , Joerg Vollrath
- 申请人: Randall Rooney , Joerg Vollrath
- 申请人地址: US VA Sandston
- 专利权人: Infineon Technologies Richmond LP
- 当前专利权人: Infineon Technologies Richmond LP
- 当前专利权人地址: US VA Sandston
- 代理机构: Brinks Hofer Gilson & Lione
- 主分类号: G11C29/00
- IPC分类号: G11C29/00
摘要:
According to an embodiment of the present invention, a method is provided for determining a fail string for a device. The method includes determining a test pattern for a portion of an address space wherein the test pattern includes at least one address in the address space and the portion of the address space includes at least one x address and at least one y addresses. The method executes a test a plurality of times for each test pattern, wherein every combination of the test pattern is tested, wherein the combinations include each address held at a first potential for at least a first test and a second potential for at least a second test. The method includes determining a fail string for the device including pass/fail results for the test pattern, and combining the pass/fail results in the fail string.
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