发明授权
- 专利标题: Hardware detected command-per-clock
- 专利标题(中): 硬件检测每个时钟指令
-
申请号: US10749183申请日: 2003-12-30
-
公开(公告)号: US07058752B2公开(公告)日: 2006-06-06
- 发明人: Suryaprasad Kareenahalli , Zohar B. Bogin , Anoop Mukker
- 申请人: Suryaprasad Kareenahalli , Zohar B. Bogin , Anoop Mukker
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: G06F12/00
- IPC分类号: G06F12/00
摘要:
A memory controller is coupled to a memory device via a memory channel. The memory controller includes a command-per-clock detection unit that compares a portion of a current address with a portion of a previous address. If there is a match, then the memory controller can continue to assert a chip select line coupled to the memory device. The command-per-clock detection unit checks to see whether only certain low-order bits of the address lines are toggling between the current and previous addresses. Additional copies of address lines for particular low-order bits are provided to the memory device to reduce loading on the low order bit address lines, allowing the low order bit address lines to toggle quickly in order to avoid the necessity of inserting a one clock period wait state. If the command-per-clock detection unit does not find a match (meaning that more than the low order address bits are toggling) then the wait state is inserted by deasserting the chip select line for a clock period.
公开/授权文献
- US20050144374A1 Hardware detected command-per-clock 公开/授权日:2005-06-30