Disclosed is a design method for plating of a printed circuit board (PCB) strip, in which a main plating line is optionally formed on a component side, a solder side, or an inner layer of the PCB strip by modifying a sub-plating line of the PCB strip used to manufacture a semiconductor chip package, and a method of manufacturing the semiconductor chip package using the same. Therefore, an excellent semiconductor chip package is manufactured without a short when the PCB strip is cut using a sawing machine because misalignment of main plating lines of the solder side and the component side of the PCB strip is avoided, and an interval between PCB units is reduced to desirably increase the number of PCB units in the PCB strip without the short when the PCB strip is cut.