A ferroelectric memory device and a method of fabricating the same are provided. The device includes a substrate where a conductive region is formed and an interlayer insulating layer. The interlayer insulating layer is stacked on the substrate and has a contact hole exposing the conductive region. The contact hole is filled with a contact plug having a projection over the interlayer insulating layer. The projection of the contact plug is covered with a capacitor including a lower electrode, a ferroelectric layer pattern, and an upper electrode. A width of the projection is preferably greater than that of the contact hole and smaller than that of the lower electrode. The method includes forming lower and upper interlayer insulating layers on a substrate where a conductive region is formed. The lower and upper interlayer insulating layers have a contact hole exposing the conductive region. After forming a conductive contact plug filling the contact hole, the upper interlayer insulating layer is removed to expose the lower interlayer insulating layer. Thus, an upper portion of the contact plug that is higher than the lower interlayer insulating layer is projected. Continuously, a lower electrode, a ferroelectric layer pattern, and an upper electrode sequentially cover the projected contact plug to form a capacitor. The upper interlayer insulating layer is preferably made of a material having an etch selectivity with respect to the lower interlayer insulating layer. The contact hole is preferably formed such that a width of the contact hole formed in the upper interlayer insulating layer is greater than that of the contact hole formed in the lower interlayer insulating layer.