公开(公告)号：US08873274B2

公开(公告)日：2014-10-28

申请号：US13862918

申请日：2013-04-15

Applicant: In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

Inventor： In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

IPC: G11C11/00

CPC classification number: H01L45/04 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

Abstract translation: 存储单元包括衬底中的插塞式第一电极，设置在第一电极上的磁阻存储元件，以及设置在与第一电极相对的磁阻存储元件上的第二电极。 第二电极具有与磁阻存储元件重叠的区域，其大于第一电极和磁阻存储元件的重叠区域。 例如，第一表面可以是基本上圆形的并且具有小于第二表面的最小平面尺寸（例如，宽度）的直径。 磁阻存储元件可以包括巨磁阻材料，例如具有钙钛矿相和/或过渡金属氧化物的绝缘材料。

公开(公告)号：US20130240826A1

公开(公告)日：2013-09-19

申请号：US13862918

申请日：2013-04-15

Applicant: In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

Inventor： In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

IPC: H01L45/00

CPC classification number: H01L45/04 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

Abstract translation: 存储单元包括衬底中的插塞式第一电极，设置在第一电极上的磁阻存储元件，以及设置在与第一电极相对的磁阻存储元件上的第二电极。 第二电极具有与磁阻存储元件重叠的区域，其大于第一电极和磁阻存储元件的重叠区域。 例如，第一表面可以是基本上圆形的并且具有小于第二表面的最小平面尺寸（例如，宽度）的直径。 磁阻存储元件可以包括巨磁阻材料，例如具有钙钛矿相和/或过渡金属氧化物的绝缘材料。

公开(公告)号：US08227303B2

公开(公告)日：2012-07-24

申请号：US13173670

申请日：2011-06-30

Applicant: Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

Inventor： Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

IPC: H01L21/336

CPC classification number: H01L27/124 ,  B82Y10/00 ,  H01L27/095 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/45 ,  H01L29/7839 ,  H01L29/78681 ,  H01L29/7869

Abstract: A method of manufacturing a CMOS transistor can be provided by forming first and second gate electrodes on a substrate and forming a gate insulation layer on the first and second gate electrodes. A semiconductor channel material having a first conductivity type can be formed on the gate insulation layer. A pair of ohmic contacts can be formed on the semiconductor channel material such that the ohmic contacts cross over both side portions of the first gate electrode, respectively. A pair of Schottky contacts can be formed on the semiconductor channel material such that the Schottky contacts cross over both side portions of the second gate electrode, respectively.

Abstract translation: 可以通过在衬底上形成第一和第二栅电极并在第一和第二栅电极上形成栅极绝缘层来提供制造CMOS晶体管的方法。 可以在栅极绝缘层上形成具有第一导电类型的半导体沟道材料。 可以在半导体沟道材料上形成一对欧姆接触，使得欧姆接触分别跨过第一栅电极的两侧部分。 可以在半导体沟道材料上形成一对肖特基触点，使得肖特基触点分别跨过第二栅电极的两侧部分。

公开(公告)号：US20120149156A1

公开(公告)日：2012-06-14

申请号：US13404051

申请日：2012-02-24

Applicant: Moon-Sook Lee

Inventor： Moon-Sook Lee

IPC: H01L21/336 ,  B82Y40/00

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/0673 ,  H01L29/66825 ,  H01L29/7881 ,  Y10S977/813 ,  Y10S977/842 ,  Y10S977/843 ,  Y10S977/89 ,  Y10S977/891

Abstract: A plurality of nanowires is grown on a first substrate in a first direction perpendicular to the first substrate. An insulation layer covering the nanowires is formed on the first substrate to define a nanowire block including the nanowires and the insulation layer. The nanowire block is moved so that each of the nanowires is arranged in a second direction parallel to the first substrate. The insulation layer is partially removed to partially expose the nanowires. A gate line covering the exposed nanowires is formed. Impurities are implanted into portions of the nanowires adjacent to the gate line.

Abstract translation: 多个纳米线在与第一基板垂直的第一方向上在第一基板上生长。 覆盖纳米线的绝缘层形成在第一基板上，以限定包括纳米线和绝缘层的纳米线块。 移动纳米线块，使得每个纳米线沿平行于第一基底的第二方向排列。 绝缘层被部分去除以部分地暴露纳米线。 形成覆盖暴露的纳米线的栅极线。 将杂质注入到与栅极线相邻的纳米线的部分中。

公开(公告)号：US08148212B2

公开(公告)日：2012-04-03

申请号：US12313887

申请日：2008-11-25

Applicant: Moon-Sook Lee

Inventor： Moon-Sook Lee

IPC: H01L21/44 ,  H01L21/336

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/0673 ,  H01L29/66825 ,  H01L29/7881 ,  Y10S977/813 ,  Y10S977/842 ,  Y10S977/843 ,  Y10S977/89 ,  Y10S977/891

Abstract: A plurality of nanowires is grown on a first substrate in a first direction perpendicular to the first substrate. An insulation layer covering the nanowires is formed on the first substrate to define a nanowire block including the nanowires and the insulation layer. The nanowire block is moved so that each of the nanowires is arranged in a second direction parallel to the first substrate. The insulation layer is partially removed to partially expose the nanowires. A gate line covering the exposed nanowires is formed. Impurities are implanted into portions of the nanowires adjacent to the gate line.

公开(公告)号：US20110294268A1

公开(公告)日：2011-12-01

申请号：US13204785

申请日：2011-08-08

Applicant: Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

Inventor： Sang-Hun Jeon ,  Moon-Sook Lee ,  Byeong-Ok Cho

IPC: H01L21/336

CPC classification number: H01L29/41733 ,  H01L27/1292 ,  H01L29/42384

Abstract: A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.

Abstract translation: 薄膜晶体管包括具有栅电极，栅极绝缘层和沟道层的层结构。 源极线可以接触沟道层，并且可以沿着与栅电极交叉的方向延伸。 源极线可以部分地与栅电极重叠，使得与栅电极重叠的源极线的两侧可以完全位于栅电极的两侧之间。 漏极线可以与沟道层接触并且可以与源极线隔开通道长度。 漏极线可以具有与源极线对称的结构。 可以减小栅电极，源极线和漏极线之间的重叠区域，使得薄膜晶体管可以确保高的截止频率。

公开(公告)号：US20110204314A1

公开(公告)日：2011-08-25

申请号：US13100702

申请日：2011-05-04

Applicant: In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

Inventor： In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

IPC: H01L45/00

CPC classification number: H01L45/04 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

Abstract translation: 存储单元包括衬底中的插塞式第一电极，设置在第一电极上的磁阻存储元件，以及设置在与第一电极相对的磁阻存储元件上的第二电极。 第二电极具有与磁阻存储元件重叠的区域，其大于第一电极和磁阻存储元件的重叠区域。 例如，第一表面可以是基本上圆形的并且具有小于第二表面的最小平面尺寸（例如，宽度）的直径。 磁阻存储元件可以包括巨磁阻材料，例如具有钙钛矿相和/或过渡金属氧化物的绝缘材料。

公开(公告)号：US07961496B2

公开(公告)日：2011-06-14

申请号：US12612187

申请日：2009-11-04

Applicant: In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

Inventor： In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

IPC: G11C11/00

CPC classification number: H01L45/04 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

Abstract translation: 存储单元包括衬底中的插塞式第一电极，设置在第一电极上的磁阻存储元件，以及设置在与第一电极相对的磁阻存储元件上的第二电极。 第二电极具有与磁阻存储元件重叠的区域，其大于第一电极和磁阻存储元件的重叠区域。 例如，第一表面可以是基本上圆形的并且具有小于第二表面的最小平面尺寸（例如，宽度）的直径。 磁阻存储元件可以包括巨磁阻材料，例如具有钙钛矿相和/或过渡金属氧化物的绝缘材料。

公开(公告)号：US07955869B2

公开(公告)日：2011-06-07

申请号：US12381987

申请日：2009-03-18

Applicant: Yasue Takahiro ,  Byeong-Ok Cho ,  Moon-Sook Lee

Inventor： Yasue Takahiro ,  Byeong-Ok Cho ,  Moon-Sook Lee

IPC: H01L21/00

CPC classification number: H01L27/11507 ,  B82Y10/00 ,  H01L21/28291 ,  H01L27/101 ,  H01L27/285 ,  H01L28/40 ,  H01L51/0004

Abstract: Nonvolatile memory devices and methods of fabricating the same are provided. In some embodiments, a nonvolatile memory device includes a lower conductive member formed on an upper part of or inside a substrate, a ferroelectric organic layer formed on the lower conductive member, a protective layer formed on the ferroelectric organic layer, and an upper conductive member formed on the protective layer to cross the lower conductive member.

Abstract translation: 提供非易失性存储器件及其制造方法。 在一些实施例中，非易失性存储器件包括形成在衬底的上部或内部的下导电构件，形成在下导电构件上的铁电有机层，形成在铁电有机层上的保护层和上导电构件 形成在保护层上以穿过下导电构件。

公开(公告)号：US20100314600A1

公开(公告)日：2010-12-16

申请号：US12851268

申请日：2010-08-05

Applicant: Moon-Sook Lee ,  Byeong-Ok Cho ,  Man-Hyoung Ryoo ,  Takahiro Yasue

Inventor： Moon-Sook Lee ,  Byeong-Ok Cho ,  Man-Hyoung Ryoo ,  Takahiro Yasue

IPC: H01L45/00

CPC classification number: H01L27/11507 ,  B82Y10/00 ,  H01L27/10 ,  H01L27/1021 ,  H01L27/24

Abstract: Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes. Related memory units, methods of fabricating semiconductor devices and semiconductor devices are also provided.

Abstract translation: 提供了一种制造存储器单元的方法，包括形成多个第一纳米线结构，每个第一纳米线结构包括在第一衬底上沿与第一衬底平行的第一方向延伸的第一纳米线和包围第一纳米线的第一电极层。 第一电极层被部分地去除以在第一纳米线下方形成第一电极。 填充第一基板上形成有第一纳米线和第一电极的结构之间的空间的第一绝缘层。 在第一纳米线和第一绝缘层上形成第二电极层。 多个第二纳米线形成在第二电极层上，每个第二纳米线沿垂直于第一方向的第二方向延伸。 使用第二纳米线作为蚀刻掩模来部分蚀刻第二电极层以形成多个第二电极。 还提供了相关的存储单元，制造半导体器件和半导体器件的方法。