发明授权
US07071085B1 Predefined critical spaces in IC patterning to reduce line end pull back
有权
IC图案化中预定的关键空间，以减少线端拉回
- 专利标题： Predefined critical spaces in IC patterning to reduce line end pull back
- 专利标题（中）： IC图案化中预定的关键空间，以减少线端拉回
-
申请号： US10852876申请日： 2004-05-25
-
公开(公告)号： US07071085B1公开(公告)日： 2006-07-04
- 发明人: Todd P. Lukanc , Luigi Capodieci , Christopher A. Spence , Joerg Reiss , Sarah N. McGowan
- 申请人： Todd P. Lukanc , Luigi Capodieci , Christopher A. Spence , Joerg Reiss , Sarah N. McGowan
- 申请人地址： US CA Sunnyvale
- 专利权人： Advanced Micro Devices, Inc.
- 当前专利权人： Advanced Micro Devices, Inc.
- 当前专利权人地址： US CA Sunnyvale
- 代理机构： Renner, Otto, Boisselle & Sklar, LLP
- 主分类号： H01L21/475
- IPC分类号： H01L21/475
摘要：
The invention includes an apparatus and a method of manufacturing such apparatus including the steps of: forming a layer to be patterned, forming a photosensitive layer over the layer to be patterned, patterning the photosensitive layer to form a pattern including a horizontal line and a vertical line without a space therebetween, transferring the pattern to the layer to be patterned, forming a second photosensitive layer over the pattern, patterning the second photosensitive layer to form a second pattern including a space aligned between the horizontal line and the vertical line, and transferring the second pattern to the layer to be patterned to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a width dimension achievable at a resolution limit of lithography.