发明授权
- 专利标题: Semiconductor device having a power down mode
- 专利标题(中): 具有掉电模式的半导体器件
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申请号: US11084138申请日: 2005-03-21
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公开(公告)号: US07072202B2公开(公告)日: 2006-07-04
- 发明人: Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
- 申请人: Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
- 申请人地址: JP Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JP Tokyo
- 代理机构: Antonelli, Terry, Stout and Kraus, LLP.
- 优先权: JP10-98694 19980410
- 主分类号: G11C5/06
- IPC分类号: G11C5/06
摘要:
A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
公开/授权文献
- US20050231991A1 Semiconductor device having a power down mode 公开/授权日:2005-10-20
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