发明授权
- 专利标题: Memory system having fast and slow data reading mechanisms
- 专利标题(中): 内存系统具有快速和慢速的数据读取机制
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申请号: US11150585申请日: 2005-06-13
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公开(公告)号: US07072229B2公开(公告)日: 2006-07-04
- 发明人: Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , Dennis Michael Sylvester , Krisztian Flautner
- 申请人: Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge , Dennis Michael Sylvester , Krisztian Flautner
- 申请人地址: GB Cambridge US MI Ann Arbor
- 专利权人: ARM Limited,The Regents of the University of Michigan
- 当前专利权人: ARM Limited,The Regents of the University of Michigan
- 当前专利权人地址: GB Cambridge US MI Ann Arbor
- 代理机构: Nixon & Vanderhye P.C.
- 主分类号: G11C7/00
- IPC分类号: G11C7/00
摘要:
There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.
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