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公开(公告)号：US08505002B2
公开(公告)日：2013-08-06
申请号：US11905160
申请日：2007-09-27
申请人： Sami Yehia , Krisztian Flautner , Nathan Clark , Amir Hormati , Scott Mahlke
发明人： Sami Yehia , Krisztian Flautner , Nathan Clark , Amir Hormati , Scott Mahlke
IPC分类号： G06F9/45
CPC分类号： G06F9/30054 , G06F9/30032 , G06F9/30036 , G06F9/30174 , G06F9/3802 , G06F9/3808 , G06F9/3885 , G06F9/3887 , G06F9/45516
摘要： A data processing system is provided having a processor and analysing circuitry for identifying a SIMD instruction associated with a first SIMD instruction set and replacing it by a functionally-equivalent scalar representation and marking that functionally-equivalent scalar representation. The marked functionally-equivalent scalar representation is dynamically translated using translation circuitry upon execution of the program to generate one or more corresponding translated instructions corresponding to a instruction set architecture different from the first SIMD architecture corresponding to the identified SIMD instruction.
摘要翻译： 提供了一种数据处理系统，其具有处理器和分析电路，用于识别与第一SIMD指令集相关联的SIMD指令，并通过功能等效的标量表示代替它并标记该功能等效的标量表示。 标记的功能等效标量表示在执行程序时使用转换电路进行动态转换，以生成对应于与所识别的SIMD指令相对应的第一SIMD架构不同的指令集架构的一个或多个相应的转换指令。
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公开(公告)号：US08185786B2
公开(公告)日：2012-05-22
申请号：US12923911
申请日：2010-10-13
IPC分类号： G06F11/00
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic, a non-delayed signal-capture element, a delayed signal-capture element and a comparator. The non-delayed signal-capture element captures an output from the processing logic at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element also captures a value from the processing logic. An error detection circuit and error correction circuit detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator. The comparator compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译： 集成电路包括多个处理级，每个处理级包括处理逻辑，非延迟信号捕获元件，延迟信号捕获元件和比较器。 非延迟信号捕获元件在非延迟捕获时间捕获来自处理逻辑的输出。 在稍后的延迟捕获时间，延迟信号捕获元件还捕获来自处理逻辑的值。 误差检测电路和误差校正电路检测并校正延迟值中的随机误差，并向比较器提供经错误检测的延迟值。 比较器比较错误检查的延迟值和非延迟值，如果它们不相等，则表示非延迟值被捕获太早，应由错误检查的延迟值替换。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。
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3.发明授权Performance level selection in a data processing system by combining a plurality of performance requests 有权通过组合多个性能请求在数据处理系统中进行性能级别选择公开(公告)号：US07512820B2
公开(公告)日：2009-03-31
申请号：US11520007
申请日：2006-09-13
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , Y02D10/126
摘要： Performance level selection is carried out by calculating a plurality of performance requests using a plurality of performance request calculating algorithms, combining those different performance requests to form a global performance request and then selecting a performance level in dependence upon the global performance level request. The performance request calculating algorithms can be arranged in a hierarchy with their performance requests evaluated in a sequence starting from the least dominant position in the hierarchy and moving through to the most dominant position in the hierarchy. Commands may accompany each performance level request to specify how it should be combined with other performance level requests.
摘要翻译： 通过使用多个性能请求计算算法来计算多个性能请求来执行性能级别选择，组合那些不同的性能请求以形成全局性能请求，然后根据全局性能级别请求选择性能级别。 可以将性能请求计算算法排列在层次结构中，其性能请求以从层次结构中的最低主导位置开始的序列进行评估，并且移动到层次结构中最主要的位置。 命令可以伴随每个性能级别请求来指定如何与其他性能级别请求组合。
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公开(公告)号：US20090049331A1
公开(公告)日：2009-02-19
申请号：US11887106
申请日：2005-10-03
IPC分类号： G06F11/20
CPC分类号： G06F11/261 , G06F17/5045 , Y02T10/82
摘要： A method of selecting where error detection circuits should be placed within an integrated circuit uses simulation of a reference and test design with errors injected into the test design and then fan out analysis performed upon those injected errors to identify error propagation characteristics. Thus, registers at which propagated errors are highly likely to manifest themselves or which protect key architectural state, or which protect state not otherwise protected can be identified and so an efficient deployment of error detection mechanisms achieved. Within an integrated circuit output signals from inactive circuit elements may be subject to isolation gating in dependence upon a detected current state of the integrated circuit. Thus, inactive circuit elements in which soft errors occur have inappropriate output signals gated from reaching the rest of the integrated circuit and thus reducing erroneous operation.
摘要翻译： 选择错误检测电路应放置在集成电路中的方法，使用注入到测试设计中的错误的参考和测试设计的仿真，然后扇出对这些注入错误进行的分析，以识别误差传播特性。 因此，可以识别传播错误很可能表现自身或者保护关键体系结构状态或哪个保护状态没有被其他方式保护的寄存器，从而实现错误检测机制的有效部署。 在集成电路内，根据检测到的集成电路的当前状态，来自非活动电路元件的输出信号可能经受隔离门控。 因此，出现软错误的无效电路元件具有不适当的输出信号，从而不能到达集成电路的其余部分，从而减少错误的操作。
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公开(公告)号：US07434072B2
公开(公告)日：2008-10-07
申请号：US11113310
申请日：2005-04-25
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Power management control software including power management policies is provided with those policies divided into observation code 18, 20, 22 and response code 26, 28, 30. When predetermined execution points 10, 12 within the operating system 2 are reached registered observation code 18, 20 for those execution points 10, 12 is triggered to be executed and serves to store event data within an event data store 24. At another time independent of the execution points 10, 12, the response code 26, 28, 30 is executed to read the event data from the event data store 24 and generate power control predictions and control signals therefrom.
摘要翻译： 电力管理控制软件包括电源管理策略，分为观察码18,20,22和响应码26,28,30之间的那些策略。 当达到操作系统2内的预定执行点10,12到达注册观察码18,20时，触发执行点10,12，并用于在事件数据存储器24内存储事件数据。 在独立于执行点10,12的另一时间，执行响应代码26,28,30以从事件数据存储器24读取事件数据，并从其生成功率控制预测和控制信号。
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6.发明授权Systematic and random error detection and recovery within processing stages of an integrated circuit 有权在集成电路的处理阶段内的系统和随机的错误检测和恢复公开(公告)号：US07337356B2
公开(公告)日：2008-02-26
申请号：US10896997
申请日：2004-07-23
IPC分类号： G06F11/00
CPC分类号： G06F11/1695 , G06F9/3861 , G06F9/3869 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
摘要翻译： 集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024。 非延迟信号捕获元件1016在非延迟捕获时间捕获来自处理逻辑1014的输出。 在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。 误差检测电路1026和误差校正电路1028检测并校正延迟值中的随机误差，并将错误检测的延迟值提供给比较器1024。 比较器1024比较错误检查的延迟值和非延迟值，如果它们不相等，则表示非延迟值被捕获得太早，应该被错误检查的延迟值替换。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。
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公开(公告)号：US20060018171A1
公开(公告)日：2006-01-26
申请号：US11150585
申请日：2005-06-13
IPC分类号： G11C7/00
CPC分类号： G06F9/3869 , G06F9/3861 , G06F11/141 , G11C7/04 , G11C7/1006 , G11C7/1039 , G11C7/1045 , G11C7/22 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C2207/2281
摘要： There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.
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公开(公告)号：US20050097228A1
公开(公告)日：2005-05-05
申请号：US10687924
申请日：2003-10-20
申请人： Krisztian Flautner , Trevor Mudge , David Flynn
发明人： Krisztian Flautner , Trevor Mudge , David Flynn
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A performance counter accumulates a value by periodically adding a variable increment value representing the amount of work performed. The increment value can be varied in dependence upon the processor clock frequency and may be adjusted under hardware and/or software control.
摘要翻译： 性能计数器通过周期性地添加表示所执行的工作量的可变增量值累加值。 增量值可以根据处理器时钟频率而变化，并且可以在硬件和/或软件控制下进行调整。
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公开(公告)号：US20050034002A1
公开(公告)日：2005-02-10
申请号：US10633360
申请日：2003-08-04
申请人： Krisztian Flautner
发明人： Krisztian Flautner
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D10/24 , Y10T307/707
摘要： A multi-processing system 2 measures the degree of parallelism achieved in executing program instructions and uses this to dynamically control the clock speeds and supply voltage levels applied to different processor cores 4, 6 so as to reduce the overall amount of energy consumed by matching the processing performance achieved to the clock speeds and voltage levels used.
摘要翻译： 多处理系统2测量在执行程序指令中实现的并行度，并且使用它来动态地控制施加到不同处理器核心4,6的时钟速度和电源电压电平，以便通过匹配 处理性能达到了使用的时钟速度和电压电平。
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公开(公告)号：US07863733B2
公开(公告)日：2011-01-04
申请号：US12007480
申请日：2008-01-10
CPC分类号： H01L25/0657 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , Y10T29/49002 , H01L2924/00
摘要： An integrated circuit 78 is formed of multiple layers of circuits 14, 16 superimposed to produce stacks of circuit blocks 2, 4. Stack control circuitry 18, 20 is associated with the input and output signals from the circuit blocks to direct these to/from the currently active circuit block(s) as appropriate. The superimposed circuit blocks 2, 4 provide redundancy for each other, both for manufacturing defect resistance and for operational redundancy, such as providing multiple modular redundancy in safety critical environments.
摘要翻译： 集成电路78由叠加的多层电路14,16形成，以产生电路块2,4的堆叠。堆叠控制电路18,20与来自电路块的输入和输出信号相关联，以将它们引导到/ 当前有效的电路块（适用）。 叠加的电路块2,4为制造缺陷电阻和操作冗余提供彼此的冗余性，例如在安全关键环境中提供多个模块冗余。
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