发明授权
US07073106B2 Test method for guaranteeing full stuck-at-fault coverage of a memory array
失效
用于确保存储器阵列的完全卡在故障覆盖的测试方法
- 专利标题: Test method for guaranteeing full stuck-at-fault coverage of a memory array
- 专利标题(中): 用于确保存储器阵列的完全卡在故障覆盖的测试方法
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申请号: US10392665申请日: 2003-03-19
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公开(公告)号: US07073106B2公开(公告)日: 2006-07-04
- 发明人: Jose A. Paredes , Philip G. Shephard, III , Timothy M. Skergan , Neil R. Vanderschaaf
- 申请人: Jose A. Paredes , Philip G. Shephard, III , Timothy M. Skergan , Neil R. Vanderschaaf
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Winstead Sechrest & Minick P.C.
- 代理商 Robert A. Voigt, Jr.; Casimer K. Salys
- 主分类号: G11C29/00
- IPC分类号: G11C29/00
摘要:
A method, computer program product and system for testing stuck-at-faults. A first register may be loaded with a first value where the first value may be written into each entry in a memory array. A second register may be loaded with a second value. A third register may be loaded with either the second value or a third value. The second and third values are pre-selected to test selector circuits for stuck-at-faults with a pattern where the pattern includes a set of bits to be inputted to selector circuits and a set of bits to be stored in the memory cells. A value stored in the n-most significant bits in both the second and third registers may be predecoded to produce a predecode value. The predecode value may be compared with the value stored in the n-most significant bits in an entry in the memory array to determine a stuck-at-fault.
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