发明授权
- 专利标题: Method of manufacturing a semiconductor integrated circuit device that includes forming dummy patterns in an isolation region prior to filling with insulating material
- 专利标题(中): 一种制造半导体集成电路器件的方法,包括在填充绝缘材料之前在隔离区域中形成虚拟图案
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申请号: US11149539申请日: 2005-06-10
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公开(公告)号: US07074691B2公开(公告)日: 2006-07-11
- 发明人: Hidenori Sato , Norio Suzuki , Akira Takamatsu , Hiroyuki Maruyama , Takeshi Saikawa , Katsuhiko Hotta , Hiroyuki Ichizoe
- 申请人: Hidenori Sato , Norio Suzuki , Akira Takamatsu , Hiroyuki Maruyama , Takeshi Saikawa , Katsuhiko Hotta , Hiroyuki Ichizoe
- 申请人地址: JP Tokyo JP Tokyo
- 专利权人: Hitachi, Ltd.,Hitachi ULSI Systems C O., Ltd.
- 当前专利权人: Hitachi, Ltd.,Hitachi ULSI Systems C O., Ltd.
- 当前专利权人地址: JP Tokyo JP Tokyo
- 代理机构: Antonelli, Terry, Stout and Kraus, LLP.
- 优先权: JP2000-012026 20000120
- 主分类号: H01L21/762
- IPC分类号: H01L21/762
摘要:
A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.
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