公开(公告)号：US20070114631A1

公开(公告)日：2007-05-24

申请号：US11653321

申请日：2007-01-16

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L29/00

CPC分类号： H01L21/76224 ,  H01L27/0207 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.

摘要翻译： 一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置， 用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽 沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。 该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对大的隔离区域中形成伪图案的步骤。

公开(公告)号：US20050148155A1

公开(公告)日：2005-07-07

申请号：US11055745

申请日：2005-02-11

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L21/76 ,  G02B17/00 ,  G02B21/00 ,  G02B23/00 ,  H01L21/302 ,  H01L21/312 ,  H01L21/316 ,  H01L21/461 ,  H01L21/762 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patterns in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited

摘要翻译： 一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置， 用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽 沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。 该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对较大的隔离区域中形成虚拟图案的步骤

公开(公告)号：US07208391B2

公开(公告)日：2007-04-24

申请号：US11149538

申请日：2005-06-10

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.

摘要翻译： 一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置， 用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽 沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。 该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对大的隔离区域中形成伪图案的步骤。

公开(公告)号：US20050239257A1

公开(公告)日：2005-10-27

申请号：US11149538

申请日：2005-06-10

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L21/76 ,  G02B17/00 ,  G02B21/00 ,  G02B23/00 ,  H01L21/302 ,  H01L21/312 ,  H01L21/316 ,  H01L21/461 ,  H01L21/762 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.

公开(公告)号：US07397104B2

公开(公告)日：2008-07-08

申请号：US10778081

申请日：2004-02-17

申请人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

发明人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

IPC分类号： H01L21/00

CPC分类号： H01L21/76229 ,  H01L21/76224 ,  H01L21/76232 ,  H01L27/10852 ,  H01L28/91

摘要： A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.

摘要翻译： 提供一种半导体集成电路器件，其包括有源区，与有源区相邻的浅槽隔离，以及形成在有源区中并具有栅极的半导体元件。 有源区的宽度和浅槽隔离的宽度的和构成栅极的栅极宽度方向上的最小间距，并且有源区的宽度被设定为大于最小间距的一半 。

公开(公告)号：US07074691B2

公开(公告)日：2006-07-11

申请号：US11149539

申请日：2005-06-10

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.

摘要翻译： 一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置， 用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽 沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。 该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对大的隔离区域中形成伪图案的步骤。

公开(公告)号：US06720234B2

公开(公告)日：2004-04-13

申请号：US10366423

申请日：2003-02-14

申请人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

发明人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/76224 ,  H01L21/76232 ,  H01L27/10852 ,  H01L28/91

摘要： Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.

摘要翻译： 通过使用氮化硅膜和侧壁间隔物作为掩模的干蚀刻将沟槽限定在具有器件隔离区的衬底中。 此后，除去位于氮化硅膜侧壁上的侧壁隔离物，并对衬底进行热氧化，由此在每个有源区的周边部分的衬底表面进行所谓的圆形处理，以便 具有凸形圆形的截面形状。

公开(公告)号：US07060589B2

公开(公告)日：2006-06-13

申请号：US11055745

申请日：2005-02-11

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patterns in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited

摘要翻译： 一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置， 用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽 沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。 该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对较大的隔离区域中形成虚拟图案的步骤

公开(公告)号：US20050237603A1

公开(公告)日：2005-10-27

申请号：US11149539

申请日：2005-06-10

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L21/76 ,  G02B17/00 ,  G02B21/00 ,  G02B23/00 ,  H01L21/302 ,  H01L21/312 ,  H01L21/316 ,  H01L21/461 ,  H01L21/762 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.

摘要翻译： 一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置， 用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽 沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。 该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对大的隔离区域中形成伪图案的步骤。

公开(公告)号：US06693008B1

公开(公告)日：2004-02-17

申请号：US09709403

申请日：2000-11-13

申请人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

发明人： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC分类号： H01L218242

CPC分类号： H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

摘要： In order to fill in an isolation trench formed on a semiconductor substrate, the isolation trench is filled up to a predetermined middle position with a coating film first, and then an insulating film formed by a CVD method is deposited thereon. Additionally, the insulating film is polished by a CMP method, for example, so as to be ground. Thus, the isolation trench is filled with stacked films of the coating film and the insulating film. Further, an electrode pattern and a dummy pattern are formed on the semiconductor substrate, and the trench formed between these patterns is filled up to a predetermined middle position in its depth direction with the coating film. Then, a remaining depth portion of the trench is filled with the insulating film formed by a CVD method.

摘要翻译： 为了填充形成在半导体衬底上的隔离沟槽，首先将隔离沟槽填充到具有涂膜的预定中间位置，然后沉积通过CVD法形成的绝缘膜。 此外，例如通过CMP方法对绝缘膜进行研磨以进行研磨。 因此，隔离沟槽填充有涂膜和绝缘膜的堆叠膜。 此外，在半导体衬底上形成电极图案和虚拟图案，并且在这些图案之间形成的沟槽在其深度方向上与涂膜填充到预定的中间位置。 然后，用CVD法形成的绝缘膜填充沟槽的剩余深度部分。