Invention Grant
US07079423B1 Method for programming dual bit memory devices to reduce complementary bit disturbance
有权
用于编程双位存储器件以减少互补位干扰的方法
- Patent Title: Method for programming dual bit memory devices to reduce complementary bit disturbance
- Patent Title (中): 用于编程双位存储器件以减少互补位干扰的方法
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Application No.: US10896299Application Date: 2004-07-20
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Publication No.: US07079423B1Publication Date: 2006-07-18
- Inventor: Satoshi Torii
- Applicant: Satoshi Torii
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc
- Current Assignee: Advanced Micro Devices, Inc
- Current Assignee Address: US CA Sunnyvale
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
The present invention provides a method for programming a selected bit in a memory cell of a non-volatile dual bit flash memory device. The method includes applying a positive voltage to a bit line associated with the selected bit and applying another positive voltage to a word line associated with the selected bit. Next, a positive voltage is applied to a second bit line associated with a complementary bit that shares the memory cell with the selected bit. A positive voltage is also applied to a third bit line that is adjacent to the second bit line and removed from the bit line associated with the selected bit by the second bit line. Applying a negative voltage to the word line then erases the complementary bit, but not its adjacent non-selected bit. The programming cycle is repeated until a desired threshold voltage is obtained.
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