Invention Grant
- Patent Title: Concurrent measurement of critical dimension and overlay in semiconductor manufacturing
- Patent Title (中): 半导体制造中临界尺寸和覆盖层并行测量
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Application No.: US10379738Application Date: 2003-03-05
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Publication No.: US07080330B1Publication Date: 2006-07-18
- Inventor: Bryan Choo , Bharath Rangarajan , Bhanwar Singh , Carmen Morales
- Applicant: Bryan Choo , Bharath Rangarajan , Bhanwar Singh , Carmen Morales
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Amin & Turocy, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. One or more structures formed on a wafer matriculating through the process facilitate concurrent measurement of critical dimensions and overlay via scatterometry or a scanning electron microscope (SEM). The concurrent measurements mitigate fabrication inefficiencies, thereby reducing time and real estate required for the fabrication process. The measurements can be utilized to generate feedback and/or feed-forward data to selectively control one or more fabrication components and/or operating parameters associated therewith to achieve desired critical dimensions and to mitigate overlay error.
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