公开(公告)号：US5977542A

公开(公告)日：1999-11-02

申请号：US927971

申请日：1997-09-11

Applicant: Bhanwar Singh ,  Subash Gupta ,  Bryan Choo

Inventor： Bhanwar Singh ,  Subash Gupta ,  Bryan Choo

IPC: G03F7/40 ,  H05H3/00 ,  H01J37/38

CPC classification number: G03F7/40

Abstract: An integrated circuit manufacturing process for substantially eliminating negative electrostatic charge on a wafer surface after resist processing, comprising contacting the wafer with a dilute electrolyte solution having positive ions, restores the fidelity of CD's as measured by low-voltage SEM'S.

Abstract translation: 一种用于在抗蚀剂处理之后基本上消除晶片表面上的负静电电荷的集成电路制造方法，包括使晶片与具有正离子的稀释电解质溶液接触，通过低电压扫描电镜测量来恢复CD的保真度。

公开(公告)号：US08089113B2

公开(公告)日：2012-01-03

申请号：US11633929

申请日：2006-12-05

Applicant: Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael VanBuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffrey A. Shields

Inventor： Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael VanBuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffrey A. Shields

IPC: H01L29/94 ,  H01L27/108

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1666

Abstract: The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.

Abstract translation: 制造存储器件的本方法包括以下步骤：提供电介质层，在电介质层中提供开口，在电介质层的开口中提供第一导电体，在开口中提供开关体，并提供第二 导电体在开口处。

公开(公告)号：US20120276706A1

公开(公告)日：2012-11-01

申请号：US13529284

申请日：2012-06-21

Applicant: Suzette K. PANGRLE ,  Steven AVANZINO ,  Sameer HADDAD ,  Michael VANBUSKIRK ,  Manuj RATHOR ,  James XIE ,  Kevin SONG ,  Christie MARRIAN ,  Bryan CHOO ,  Fei WANG ,  Jeffery A. SHIELDS

Inventor： Suzette K. PANGRLE ,  Steven AVANZINO ,  Sameer HADDAD ,  Michael VANBUSKIRK ,  Manuj RATHOR ,  James XIE ,  Kevin SONG ,  Christie MARRIAN ,  Bryan CHOO ,  Fei WANG ,  Jeffery A. SHIELDS

IPC: H01L21/02

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675 ,  H01L45/1683

Abstract: A present method of fabricating a memory device includes the steps of providing a dielectric layer;, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body Filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.

Abstract translation: 本发明的制造存储器件的方法包括以下步骤：提供电介质层;在电介质层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体 填充开口，并在开关体上设置第二导电体。 在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

公开(公告)号：US08232175B2

公开(公告)日：2012-07-31

申请号：US11521204

申请日：2006-09-14

Applicant: Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael VanBuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffrey A. Shields

Inventor： Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael VanBuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffrey A. Shields

IPC: H01L21/20

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675 ,  H01L45/1683

Abstract: A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.

Abstract translation: 制造存储器件的现有方法包括以下步骤：提供电介质层，在介电层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充物 并且在开关体上设置第二导电体。 在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

公开(公告)号：US20080132068A1

公开(公告)日：2008-06-05

申请号：US11633929

申请日：2006-12-05

Applicant: Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael VanBuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffrey A. Shields

Inventor： Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael VanBuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffrey A. Shields

IPC: H01L21/44

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1666

Abstract: The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.

Abstract translation: 制造存储器件的本方法包括以下步骤：提供电介质层，在电介质层中提供开口，在电介质层的开口中提供第一导电体，在开口中提供开关体，并提供第二 导电体在开口处。

公开(公告)号：US07173648B1

公开(公告)日：2007-02-06

申请号：US09553841

申请日：2000-04-21

Applicant: Khoi Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Bryan Choo

Inventor： Khoi Phan ,  Bharath Rangarajan ,  Bhanwar Singh ,  Bryan Choo

IPC: H04N7/18 ,  G01N21/00

CPC classification number: G01N21/9501 ,  G01N21/8803 ,  G01N2021/889

Abstract: The present invention relates to visually monitoring an interior portion of a processing chamber in a semiconductor processing system. An image collector collects images of the interior of the chamber and provides an image signal indicative of a visual representation of the interior of the chamber. A viewing station receives the image signal and displays a visual representation of the interior of the chamber.

Abstract translation: 本发明涉及在半导体处理系统中视觉监测处理室的内部部分。 图像收集器收集室内部的图像，并提供指示室内部的视觉表示的图像信号。 观察台接收图像信号并显示室内部的视觉表示。

公开(公告)号：US07468296B1

公开(公告)日：2008-12-23

申请号：US11290787

申请日：2005-11-30

Applicant: Ercan Adem ,  Matthew Buynoski ,  Robert Chiu ,  Bryan Choo ,  Calvin Gabriel ,  Joong Jeon ,  David Matsumoto ,  Jeffrey Shields ,  Bhanwar Singh ,  Winny Stockwell ,  Wen Yu

Inventor： Ercan Adem ,  Matthew Buynoski ,  Robert Chiu ,  Bryan Choo ,  Calvin Gabriel ,  Joong Jeon ,  David Matsumoto ,  Jeffrey Shields ,  Bhanwar Singh ,  Winny Stockwell ,  Wen Yu

IPC: H01L21/8234 ,  H01L27/10

CPC classification number: H01L27/1021

Abstract: In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.

Abstract translation: 在制造电子结构时，提供基板，并且在基板上设置第一阻挡层。 锗薄膜二极管设置在第一阻挡层上，第二阻挡层设置在锗薄膜二极管上。 存储器件设置在第二阻挡层上并连接到第二阻挡层。

公开(公告)号：US20080123401A1

公开(公告)日：2008-05-29

申请号：US11521204

申请日：2006-09-14

Applicant: Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael VanBuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffrey A. Shields

Inventor： Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael VanBuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffrey A. Shields

IPC: G11C11/34 ,  H01L21/44

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675 ,  H01L45/1683

Abstract: A present method of fabricating a memory device includes the steps of providing a dielectric layer;, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.

Abstract translation: 本发明的制造存储器件的方法包括以下步骤：提供电介质层;在电介质层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体 填充开口，并且在开关体上提供第二导电体。 在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

公开(公告)号：US09343666B2

公开(公告)日：2016-05-17

申请号：US13529284

申请日：2012-06-21

Applicant: Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael Vanbuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffery A. Shields

Inventor： Suzette K. Pangrle ,  Steven Avanzino ,  Sameer Haddad ,  Michael Vanbuskirk ,  Manuj Rathor ,  James Xie ,  Kevin Song ,  Christie Marrian ,  Bryan Choo ,  Fei Wang ,  Jeffery A. Shields

IPC: H01L21/20 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675 ,  H01L45/1683

Abstract: A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.

Abstract translation: 制造存储器件的现有方法包括以下步骤：提供电介质层，在电介质层中提供开口，在开口中提供第一导电体，在开口中提供开关体，第一导电体和开关体填充物 并且在开关体上设置第二导电体。 在替代实施例中，在第一介电层上提供第二电介质层，并且开关体设置在第二电介质层的开口中。

公开(公告)号：US07080330B1

公开(公告)日：2006-07-18

申请号：US10379738

申请日：2003-03-05

Applicant: Bryan Choo ,  Bharath Rangarajan ,  Bhanwar Singh ,  Carmen Morales

Inventor： Bryan Choo ,  Bharath Rangarajan ,  Bhanwar Singh ,  Carmen Morales

IPC: G06F17/50

CPC classification number: G03F7/70633 ,  G01N21/4788 ,  G01N21/956 ,  G03F7/70625

Abstract: A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. One or more structures formed on a wafer matriculating through the process facilitate concurrent measurement of critical dimensions and overlay via scatterometry or a scanning electron microscope (SEM). The concurrent measurements mitigate fabrication inefficiencies, thereby reducing time and real estate required for the fabrication process. The measurements can be utilized to generate feedback and/or feed-forward data to selectively control one or more fabrication components and/or operating parameters associated therewith to achieve desired critical dimensions and to mitigate overlay error.

Abstract translation: 公开了用于监测和控制半导体制造工艺的系统和方法。 通过该过程形成的晶片上形成的一个或多个结构便于同时测量临界尺寸并通过散射测量法或扫描电子显微镜（SEM）覆盖。 同时测量可减轻制造效率低下，从而减少制造过程所需的时间和空间。 可以利用这些测量来产生反馈和/或前馈数据，以选择性地控制一个或多个制造部件和/或与之相关联的操作参数以实现所需的临界尺寸并减轻重叠误差。