发明授权
- 专利标题: Memory array with low power bit line precharge
- 专利标题(中): 具有低功耗位线预充电的存储器阵列
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申请号: US11003092申请日: 2004-12-03
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公开(公告)号: US07082061B2公开(公告)日: 2006-07-25
- 发明人: Sheree Chou , Lung-Yi Chueh , Yu-Shen Lin
- 申请人: Sheree Chou , Lung-Yi Chueh , Yu-Shen Lin
- 申请人地址: TW Hsinchu
- 专利权人: Macronix International Co., Ltd.
- 当前专利权人: Macronix International Co., Ltd.
- 当前专利权人地址: TW Hsinchu
- 代理机构: Haynes Beffel & Wolfeld
- 代理商 Mark A. Haynes
- 主分类号: G11C7/00
- IPC分类号: G11C7/00 ; G11C16/06
摘要:
An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Clamp transistors are coupled to respective bit lines in the array, and adapted to prevent voltage on the respective bit lines from exceeding a target level. A comparator has an input coupled to the reference bit line and an output coupled to the clamp transistors on the plurality of bit lines. The comparator generates a bias voltage which turns on the clamp transistors at a first bias level when the reference bit line has a voltage below the target level, and a second bias level, which is lower than the first bias level, when the reference bit line has a voltage near the target level.
公开/授权文献
- US20060120174A1 MEMORY ARRAY WITH LOW POWER BIT LINE PRECHARGE 公开/授权日:2006-06-08
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