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公开(公告)号：US20060120174A1
公开(公告)日：2006-06-08
申请号：US11003092
申请日：2004-12-03
申请人： Sheree Chou , Lung-Yi Chueh , Yu-Shen Lin
发明人： Sheree Chou , Lung-Yi Chueh , Yu-Shen Lin
IPC分类号： G11C7/10
摘要： An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Clamp transistors are coupled to respective bit lines in the array, and adapted to prevent voltage on the respective bit lines from exceeding a target level. A comparator has an input coupled to the reference bit line and an output coupled to the clamp transistors on the plurality of bit lines. The comparator generates a bias voltage which turns on the clamp transistors at a first bias level when the reference bit line has a voltage below the target level, and a second bias level, which is lower than the first bias level, when the reference bit line has a voltage near the target level.
摘要翻译： 提供具有额外的存储单元列和参考位线的集成电路存储器阵列，其中参考位线用作用于阵列中的位线的共享预充电和钳位控制的参考。 夹持晶体管耦合到阵列中的相应位线，并且适于防止相应位线上的电压超过目标电平。 比较器具有耦合到参考位线的输入端和耦合到多个位线上的钳位晶体管的输出。 比较器产生偏置电压，当参考位线具有低于目标电平的电压时，将钳位晶体管导通到第一偏置电平，并且当参考位线 具有接近目标水平的电压。
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公开(公告)号：US07082061B2
公开(公告)日：2006-07-25
申请号：US11003092
申请日：2004-12-03
申请人： Sheree Chou , Lung-Yi Chueh , Yu-Shen Lin
发明人： Sheree Chou , Lung-Yi Chueh , Yu-Shen Lin
摘要： An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Clamp transistors are coupled to respective bit lines in the array, and adapted to prevent voltage on the respective bit lines from exceeding a target level. A comparator has an input coupled to the reference bit line and an output coupled to the clamp transistors on the plurality of bit lines. The comparator generates a bias voltage which turns on the clamp transistors at a first bias level when the reference bit line has a voltage below the target level, and a second bias level, which is lower than the first bias level, when the reference bit line has a voltage near the target level.
摘要翻译： 提供具有额外的存储单元列和参考位线的集成电路存储器阵列，其中参考位线用作用于阵列中的位线的共享预充电和钳位控制的参考。 夹持晶体管耦合到阵列中的相应位线，并且适于防止相应位线上的电压超过目标电平。 比较器具有耦合到参考位线的输入端和耦合到多个位线上的钳位晶体管的输出。 比较器产生偏置电压，当参考位线具有低于目标电平的电压时，将钳位晶体管导通到第一偏置电平，并且当参考位线 具有接近目标水平的电压。
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公开(公告)号：US20060104098A1
公开(公告)日：2006-05-18
申请号：US11286204
申请日：2005-11-23
申请人： Lung-Yi Chueh , Yu-Shen Lin
发明人： Lung-Yi Chueh , Yu-Shen Lin
IPC分类号： H02M3/18
CPC分类号： H02M3/073 , H02M1/143 , H02M1/15 , H02M2003/075
摘要： A voltage-regulating device for charge pump is disclosed. The charge pump outputs an output voltage according to the operation of at least one clock signal. The voltage-regulating device includes at least one voltage regulating capacitor and at least inverter. The inverter is for receiving the clock signal and outputting an inverse clock signal accordingly. The voltage regulating capacitor has one terminal coupled to the output voltage and the other terminal coupled to the inverter for receiving the inverse clock signal. The width of a PMOS transistor is different from the width of an NMOS transistor in the inverter.
摘要翻译： 公开了一种用于电荷泵的电压调节装置。 电荷泵根据至少一个时钟信号的工作输出输出电压。 电压调节装置至少包括一个电压调节电容器和至少一个逆变器。 逆变器用于接收时钟信号并相应地输出反相时钟信号。 电压调节电容器具有耦合到输出电压的一个端子，而耦合到反相器的另一个端子用于接收逆时钟信号。 PMOS晶体管的宽度与逆变器中的NMOS晶体管的宽度不同。
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公开(公告)号：US07227764B2
公开(公告)日：2007-06-05
申请号：US11286204
申请日：2005-11-23
申请人： Lung-Yi Chueh , Yu-Shen Lin
发明人： Lung-Yi Chueh , Yu-Shen Lin
CPC分类号： H02M3/073 , H02M1/143 , H02M1/15 , H02M2003/075
摘要： A voltage-regulating device for charge pump is disclosed. The charge pump outputs an output voltage according to the operation of at least one clock signal. The voltage-regulating device includes at least one voltage regulating capacitor and at least inverter. The inverter is for receiving the clock signal and outputting an inverse clock signal accordingly. The voltage regulating capacitor has one terminal coupled to the output voltage and the other terminal coupled to the inverter for receiving the inverse clock signal. The width of a PMOS transistor is different from the width of an NMOS transistor in the inverter.
摘要翻译： 公开了一种用于电荷泵的电压调节装置。 电荷泵根据至少一个时钟信号的工作输出输出电压。 电压调节装置至少包括一个电压调节电容器和至少一个逆变器。 逆变器用于接收时钟信号并相应地输出反相时钟信号。 电压调节电容器具有耦合到输出电压的一个端子，而耦合到反相器的另一个端子用于接收逆时钟信号。 PMOS晶体管的宽度与逆变器中的NMOS晶体管的宽度不同。
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公开(公告)号：US20060120175A1
公开(公告)日：2006-06-08
申请号：US11004148
申请日：2004-12-03
申请人： Sheree Chou , Yung-Feng Lin , Yu-Shen Lin
发明人： Sheree Chou , Yung-Feng Lin , Yu-Shen Lin
IPC分类号： G11C7/10
摘要： An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Precharge transistors are coupled to respective bit lines in the array, and adapted to precharge voltage on the respective bit lines to near a target level. A detector has an input coupled to the reference bit line and an output coupled to the precharge transistors on the plurality of bit lines. The detector generates a precharge signal which turns off the precharge transistors when the reference bit line has a voltage near the target level, and turns on the precharge transistors when the reference bit line has a voltage below the target level.
摘要翻译： 提供具有额外的存储单元列和参考位线的集成电路存储器阵列，其中参考位线用作用于阵列中的位线的共享预充电和钳位控制的参考。 预充电晶体管耦合到阵列中的相应位线，并且适于将各个位线上的电压预充电到接近目标电平。 检测器具有耦合到参考位线的输入端和耦合到多个位线上的预充电晶体管的输出。 当参考位线具有接近目标电平的电压时，检测器产生预充电晶体管，当基准位线具有低于目标电平的电压时，该预充电信号导通预充电晶体管。
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公开(公告)号：US07082069B2
公开(公告)日：2006-07-25
申请号：US11004148
申请日：2004-12-03
申请人： Sheree Chou , Lung-Feng Lin , Yu-Shen Lin
发明人： Sheree Chou , Lung-Feng Lin , Yu-Shen Lin
摘要： An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Precharge transistors are coupled to respective bit lines in the array, and adapted to precharge voltage on the respective bit lines to near a target level. A detector has an input coupled to the reference bit line and an output coupled to the precharge transistors on the plurality of bit lines. The detector generates a precharge signal which turns off the precharge transistors when the reference bit line has a voltage near the target level, and turns on the precharge transistors when the reference bit line has a voltage below the target level.
摘要翻译： 提供具有额外的存储单元列和参考位线的集成电路存储器阵列，其中参考位线用作用于阵列中的位线的共享预充电和钳位控制的参考。 预充电晶体管耦合到阵列中的相应位线，并且适于将各个位线上的电压预充电到接近目标电平。 检测器具有耦合到参考位线的输入端和耦合到多个位线上的预充电晶体管的输出。 当参考位线具有接近目标电平的电压时，检测器产生预充电晶体管，当基准位线具有低于目标电平的电压时，该预充电信号导通预充电晶体管。
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7.发明授权公开(公告)号：US08274270B2
公开(公告)日：2012-09-25
申请号：US12458570
申请日：2009-07-16
申请人： Shun-An Hsieh , Yu-Shen Lin
发明人： Shun-An Hsieh , Yu-Shen Lin
CPC分类号： H03K7/08
摘要： An adaptive pulse width control power conversion device includes a pulse width adjustable pulse frequency module (PFM) control circuit, a pulse width modulation (PWM) control circuit, a PWM/PFM switching unit, a switching circuit, and a load status detection circuit. When the power conversion device is to be switched from a PWM mode to a PFM mode, pulse width of a series of PFM control signals is sequentially adjusted from a low value to a high value according to a predetermined pulse width increment until an optimum pulse width is determined and thereafter, an output voltage is supplied to a load in the PFM mode, whereby ripple of output voltage in the PFM mode can be improved and improved stability of output of the power conversion device is realized.
摘要翻译： 一种自适应脉宽控制电源转换装置，包括脉冲宽度可调脉冲频率模块（PFM）控制电路，脉宽调制（PWM）控制电路，PWM / PFM切换单元，开关电路和负载状态检测电路。 当将功率转换装置从PWM模式切换到PFM模式时，一系列PFM控制信号的脉冲宽度根据预定的脉冲宽度增量从低值依次调整为高值，直到最佳脉冲宽度 然后在PFM模式中向负载提供输出电压，从而可以提高PFM模式中的输出电压的波动，并且实现电力转换装置的输出的稳定性的提高。
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公开(公告)号：US06930926B2
公开(公告)日：2005-08-16
申请号：US10354175
申请日：2003-01-30
申请人： Yu-Shen Lin , Shin-Jang Shen , Chun-Hsiung Hung , Ho-Chun Liou , Shuo-Nan Hung
发明人： Yu-Shen Lin , Shin-Jang Shen , Chun-Hsiung Hung , Ho-Chun Liou , Shuo-Nan Hung
CPC分类号： G11C16/107 , G11C16/3468
摘要： A method for erasing a flash EEPROM. The flash EEROM includes a number of memory units. First, the flash EEPROM is pre-programmed. Second, the step of erasing the flash EEPROM is performed and the flash EEPROM is then soft-programmed. Subsequently, the final step is performed to determine if the erasing step succeeds.
摘要翻译： 一种擦除闪存EEPROM的方法。 闪存EEROM包括多个内存单元。 首先，闪存EEPROM是预编程的。 其次，执行擦除闪存EEPROM的步骤，然后对闪存EEPROM进行软编程。 随后，执行最后一步以确定擦除步骤是否成功。
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公开(公告)号：US20210030675A1
公开(公告)日：2021-02-04
申请号：US16828137
申请日：2020-03-24
申请人： C. Jeffrey Brinker , Paul N. Durfee , Jason Townson , Yu-Shen Lin , Stanley Shihyao Chou , Jacob Erstling
发明人： C. Jeffrey Brinker , Paul N. Durfee , Jason Townson , Yu-Shen Lin , Stanley Shihyao Chou , Jacob Erstling
摘要： The present disclosure is directed to methods of producing monosized protocells from monosized mesoporous silica nanoparticles (mMSNPs) and their use for targeted drug delivery formulations and systems and for biomedical applications. The present disclosure is also directed in part to a multilamellar or unilamellar protocell vaccine to deliver full length viral protein and/or plasmid encoded viral protein to antigen presenting cells (APCs) in order to induce an immunogenic response to a virus.
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公开(公告)号：USD606043S1
公开(公告)日：2009-12-15
申请号：US29311434
申请日：2009-03-16
申请人： Yu-Shen Lin
设计人： Yu-Shen Lin
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