发明授权
- 专利标题： Method and apparatus for mirroring units within a processor
- 专利标题（中）： 用于在处理器内镜像单元的方法和装置
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申请号： US10435914申请日： 2003-05-12
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公开(公告)号： US07082550B2公开(公告)日： 2006-07-25
- 发明人: Michael Billeci , Chung-Lung K. Shum , Timothy J. Slegel
- 申请人： Michael Billeci , Chung-Lung K. Shum , Timothy J. Slegel
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Cantor Colburn LLP
- 代理商 Lynn Augspurger
- 主分类号： G06F11/16
- IPC分类号： G06F11/16
摘要：
A processor responsive to a clock cycle includes a base-unit, a mirror-unit that is a duplicate instance of the base-unit, a non-duplicate-unit in signal communication with the base and mirror units, a first staging register disposed at the input to the mirror-unit for delaying the input signal thereto by at least one clock cycle, and a second staging register disposed at the output of the mirror-unit for delaying the output signal therefrom by at least one clock cycle. The non-duplicate-unit includes a comparator for comparing the output signals of the base and mirror units.
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