发明授权
US07087473B2 Method of forming conventional complementary MOS transistors and complementary heterojunction MOS transistors on common substrate
有权
在公共基板上形成常规互补MOS晶体管和互补异质结MOS晶体管的方法
- 专利标题： Method of forming conventional complementary MOS transistors and complementary heterojunction MOS transistors on common substrate
- 专利标题（中）： 在公共基板上形成常规互补MOS晶体管和互补异质结MOS晶体管的方法
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申请号： US10866093申请日： 2004-06-14
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公开(公告)号： US07087473B2公开(公告)日： 2006-08-08
- 发明人: Haruyuki Sorada , Akira Asai , Takeshi Takagi , Akira Inoue , Yoshio Kawashima
- 申请人： Haruyuki Sorada , Akira Asai , Takeshi Takagi , Akira Inoue , Yoshio Kawashima
- 申请人地址： JP Osaka
- 专利权人： Matsushita Electric Industrial Co., Ltd.
- 当前专利权人： Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址： JP Osaka
- 代理机构： McDermott Will & Emery LLP
- 优先权： JP2003-169249 20030613
- 主分类号： H01L29/80
- IPC分类号： H01L29/80
摘要：
A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.
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