公开(公告)号：US09251898B2

公开(公告)日：2016-02-02

申请号：US13983855

申请日：2012-02-07

Applicant: Koji Katayama ,  Takeshi Takagi

Inventor： Koji Katayama ,  Takeshi Takagi

IPC: G11C13/00 ,  H01L27/10 ,  H01L27/102 ,  H01L49/02 ,  H01L45/00 ,  H01L27/24 ,  G11C29/50

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/004 ,  G11C29/50008 ,  G11C2013/0045 ,  G11C2013/0083 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2418 ,  H01L28/20 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: A method for programming a nonvolatile memory element includes: decreasing a resistance value of a variable resistance element in an initial state, by applying an initialization voltage pulse to a series circuit in which a load resistor having a first resistance value is connected in series with the variable resistance element and a MSM diode; applying, after the decreasing, a write voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a second resistance value lower than the first resistance value; and applying, after the decreasing, an erase voltage pulse to the series circuit after the resistance value of the variable resistance element is changed to a third resistance value lower than the first resistance value.

Abstract translation: 一种用于非易失性存储元件的编程方法包括：通过向串联电路施加初始化电压脉冲来降低初始状态下的可变电阻元件的电阻值，其中具有第一电阻值的负载电阻器与 可变电阻元件和MSM二极管; 在可变电阻元件的电阻值变为低于第一电阻值的第二电阻值之后，在减小之后向串联电路施加写入电压脉冲; 以及在所述可变电阻元件的电阻值变为低于所述第一电阻值的第三电阻值之后，在所述减小之后向所述串联电路施加擦除电压脉冲。

公开(公告)号：US09142292B2

公开(公告)日：2015-09-22

申请号：US13982280

申请日：2012-01-31

Applicant: Yoshihiko Kanzawa ,  Takeshi Takagi

Inventor： Yoshihiko Kanzawa ,  Takeshi Takagi

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C2013/0054 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: Provided is a method for reading data from a variable resistance nonvolatile storage element, where the operation for reading data is less susceptible to a fluctuation phenomenon of resistance values in reading the data. The method includes: detecting a current value Iread that flows through the nonvolatile storage element that can be in a low resistance state RL and a high resistance state RH, with application of a fixed voltage; and determining that (i) the nonvolatile storage element is in a high resistance state when the current value Iread detected in the detecting is smaller than a current reference level Iref, and (ii) the nonvolatile storage element is in a low resistance state when the current value Iread detected in the detecting is larger than the reference level Iref, the current reference level Iref being defined by (IRL+IRH)/2

Abstract translation: 提供了一种用于从可变电阻非易失性存储元件读取数据的方法，其中用于读取数据的操作对读取数据中的电阻值的波动现象不太敏感。 该方法包括：通过施加固定电压来检测流过可以处于低电阻状态RL和高电阻状态RH的非易失性存储元件的电流值Iread; 并且当所述检测中检测到的电流值Iread小于电流参考电平Iref时，确定（i）所述非易失性存储元件处于高电阻状态，并且（ii）当所述非易失性存储元件处于低电阻状态时 在检测中检测到的电流值Iread大于参考电平Iref，当前参考电平Iref由（IRL + IRH）/ 2

公开(公告)号：US08939018B2

公开(公告)日：2015-01-27

申请号：US13122059

申请日：2009-10-02

Applicant: Toshikatsu Sakai ,  Akira Sezaki ,  Takeshi Takagi

Inventor： Toshikatsu Sakai ,  Akira Sezaki ,  Takeshi Takagi

IPC: G01N30/16 ,  G01N30/20 ,  G01N30/18 ,  G01N30/86 ,  G01N30/04

CPC classification number: G01N30/20 ,  G01N30/18 ,  G01N30/8658 ,  G01N30/8665 ,  G01N2030/042 ,  G01N2030/201 ,  G01N2030/202 ,  G01N2030/207

Abstract: An analyzing device includes a feeder connected to a container in which a sample is contained for sucking the sample from the container and feeding the sample, and a controller for performing control for feeding from the feeder to a measurer. In measuring the sample, the controller performs control so that results of a plurality of times of measurement are obtained with respect to the single container in which the sample is contained, without changing the container. This arrangement allows quick accuracy check.

Abstract translation: 分析装置包括连接到容器的进料器，在该容器中容纳样品以从容器吸取样品并进料样品;以及控制器，用于进行从进料器进给到测量器的控制。 在测量样品时，控制器执行控制，使得相对于容纳样品的单个容器获得多次测量的结果，而不改变容器。 这种安排允许快速准确的检查。

公开(公告)号：US20140029330A1

公开(公告)日：2014-01-30

申请号：US14004447

申请日：2012-03-13

Applicant: Shunsaku Muraoka ,  Satoru Mitani ,  Takeshi Takagi

Inventor： Shunsaku Muraoka ,  Satoru Mitani ,  Takeshi Takagi

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/32 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: A method for driving a nonvolatile memory element includes: a writing step of changing a variable resistance layer to a low resistance state, by applying a writing voltage pulse having a first polarity; and an erasing step of changing the variable resistance layer to a high resistance state, by applying an erasing voltage pulse having a second polarity different from the first polarity, wherein in the writing step, a first input and output terminal of a field effect transistor is a source terminal of the transistor, and when a pulse width of the writing voltage pulse is PWLR and a pulse width of the erasing voltage pulse is PWHR, PWLR and PWHR satisfy a relationship of PWLR

Abstract translation: 一种用于驱动非易失性存储元件的方法包括：通过施加具有第一极性的写入电压脉冲将可变电阻层改变为低电阻状态的写入步骤; 以及通过施加具有与第一极性不同的第二极性的擦除电压脉冲将可变电阻层改变为高电阻状态的擦除步骤，其中在写入步骤中，场效应晶体管的第一输入和输出端子是 晶体管的源极端子，并且当写入电压脉冲的脉冲宽度为PWLR且擦除电压脉冲的脉冲宽度为PWHR时，PWLR和PWHR满足PWLR

公开(公告)号：US20130308371A1

公开(公告)日：2013-11-21

申请号：US13982280

申请日：2012-01-31

Applicant: Yoshihiko Kanzawa ,  Takeshi Takagi

Inventor： Yoshihiko Kanzawa ,  Takeshi Takagi

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C2013/0054 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: Provided is a method for reading data from a variable resistance nonvolatile storage element, where the operation for reading data is less susceptible to a fluctuation phenomenon of resistance values in reading the data. The method includes: detecting a current value Iread that flows through the nonvolatile storage element that can be in a low resistance state RL and a high resistance state RH, with application of a fixed voltage; and determining that (i) the nonvolatile storage element is in a high resistance state when the current value Iread detected in the detecting is smaller than a current reference level Iref, and (ii) the nonvolatile storage element is in a low resistance state when the current value Iread detected in the detecting is larger than the reference level Iref, the current reference level Iref being defined by (IRL+IRH)/2

Abstract translation: 提供了一种用于从可变电阻非易失性存储元件读取数据的方法，其中用于读取数据的操作对读取数据中的电阻值的波动现象不太敏感。 该方法包括：通过施加固定电压来检测流过可以处于低电阻状态RL和高电阻状态RH的非易失性存储元件的电流值Iread; 并且当所述检测中检测到的电流值Iread小于电流参考电平Iref时，确定（i）所述非易失性存储元件处于高电阻状态，并且（ii）当所述非易失性存储元件处于低电阻状态时 在检测中检测到的电流值Iread大于参考电平Iref，当前参考电平Iref由（IRL + IRH）/ 2

公开(公告)号：US08553444B2

公开(公告)日：2013-10-08

申请号：US12743472

申请日：2009-08-20

Applicant: Shunsaku Muraoka ,  Yoshihiko Kanzawa ,  Satoru Mitani ,  Koji Katayama ,  Kazuhiko Shimakawa ,  Satoru Fujii ,  Takeshi Takagi

Inventor： Shunsaku Muraoka ,  Yoshihiko Kanzawa ,  Satoru Mitani ,  Koji Katayama ,  Kazuhiko Shimakawa ,  Satoru Fujii ,  Takeshi Takagi

IPC: G11C11/00

CPC classification number: H01L45/147 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (301), (ii) a variable resistance element (309) having: lower and upper electrodes (309a, 309c); and a variable resistance layer (309b) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes (309a, 309c), and (iii) a MOS transistor (317) formed on the substrate (301), wherein the variable resistance layer (309b) includes: oxygen-deficient transition metal oxide layers (309b-1, 309b-2) having compositions MOX and MOy (where x

Abstract translation: 一种可变电阻非易失性存储装置，包括：（i）半导体衬底（301），（ii）具有下电极和上电极（309a，309c）的可变电阻元件（309） 和可变电阻层（309b），其电阻值基于各自具有不同极性的电压信号而被可逆地变化并施加在电极（309a，309c）之间，以及（iii）形成在基板上的MOS晶体管 （301），其中所述可变电阻层（309b）包括：具有组成MOX和MOy（其中x

公开(公告)号：US08445885B2

公开(公告)日：2013-05-21

申请号：US13132058

申请日：2009-12-01

Applicant: Yoshihiko Kanzawa ,  Satoru Mitani ,  Zhiqiang Wei ,  Takeshi Takagi ,  Koji Katayama

Inventor： Yoshihiko Kanzawa ,  Satoru Mitani ,  Zhiqiang Wei ,  Takeshi Takagi ,  Koji Katayama

IPC: H01L29/02

CPC classification number: H01L27/101 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

Abstract: A nonvolatile memory element includes first and second electrodes, and a resistance variable layer disposed therebetween. At least one of the first and second electrodes includes a platinum-containing layer. The resistance variable layer includes a first oxygen-deficient transition metal oxide layer which is not physically in contact with the platinum-containing layer and a second oxygen-deficient transition metal oxide layer which is disposed between the first oxygen-deficient transition metal oxide layer and the platinum-containing layer and is physically in contact with the platinum-containing layer. When oxygen-deficient transition metal oxides included in the first and second oxygen-deficient transition metal oxide layers are expressed as MOx, and MOy, respectively, x

Abstract translation: 非易失性存储元件包括第一和第二电极以及设置在它们之间的电阻变化层。 第一和第二电极中的至少一个包括含铂层。 电阻变化层包括不与含铂层物理接触的第一缺氧过渡金属氧化物层和设置在第一缺氧过渡金属氧化物层和第二缺氧过渡金属氧化物层之间的第二缺氧过渡金属氧化物层 所述含铂层并且与所述含铂层物理接触。 包含在第一和第二缺氧过渡金属氧化物层中的缺氧过渡金属氧化物分别表示为MOx，MOy分别表示为x

公开(公告)号：US08405076B2

公开(公告)日：2013-03-26

申请号：US12920154

申请日：2010-02-03

Applicant: Takeki Ninomiya ,  Takeshi Takagi ,  Zhiqiang Wei

Inventor： Takeki Ninomiya ,  Takeshi Takagi ,  Zhiqiang Wei

IPC: H01L29/12

CPC classification number: H01L45/146 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/34 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1625 ,  H01L45/1675

Abstract: A nonvolatile memory element (100) includes a variable resistance layer (107) including a first metal oxide MOx and a second metal oxide MOy, and reaction energy of chemical reaction related to the first metal oxide, the second metal oxide, oxygen ions, and electrons is 2 eV or less. The chemical reaction is expressed by a formula 13, where a combination (MOx, MOy) of MOx and MOy is selected from a group including (Cr2O3, CrO3), (Co3O4, Co2O3), (Mn3O4, Mn2O3), (VO2, V2O5), (Ce2O3, CeO2), (W3O8, WO3), (Cu2O, CuO), (SnO, SnO2), (NbO2, Nb2O5), and (Ti2O3, TiO2). [Mathematical Expression 13] MOx+(y−x)O2−MOy+2(y−x)e−  (Formula 13)

Abstract translation: 非易失性存储元件（100）包括可变电阻层（107），其包括第一金属氧化物MOx和第二金属氧化物MOy，以及与第一金属氧化物，第二金属氧化物，氧离子和 电子为2eV以下。 化学反应由式13表示，其中MOx和MOy的组合（MOx，MOy）选自（Cr 2 O 3，CrO 3），（Co 3 O 4，Co 2 O 3），（Mn 3 O 4，Mn 2 O 3），（VO 2，V 2 O 5） ），（Ce 2 O 3，CeO 2），（W3O 8，WO 3），（Cu 2 O，CuO），（SnO，SnO 2），（NbO 2，Nb 2 O 5）和（Ti 2 O 3，TiO 2）。 [数学表达式13] MOx +（y-x）O2-MOy + 2（y-x）e-（式13）

公开(公告)号：US08338816B2

公开(公告)日：2012-12-25

申请号：US12682676

申请日：2008-03-31

Applicant: Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Satoru Mitani ,  Zhiqiang Wei ,  Takeshi Takagi

Inventor： Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Satoru Mitani ,  Zhiqiang Wei ,  Takeshi Takagi

IPC: H01L47/00 ,  H01L29/02 ,  H01L29/66

CPC classification number: H01L27/101 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1625

Abstract: A nonvolatile memory element of the present invention comprises a first electrode (503); a second electrode (505); and a resistance variable layer (504) which is disposed between the first electrode (503) and the second electrode (505), a resistance value of the resistance variable layer being changeable in response to electric signals which are applied between the first electrode (503) and the second electrode (505), wherein the first electrode and the second electrode comprise materials which are made of different elements.

Abstract translation: 本发明的非易失性存储元件包括第一电极（503）; 第二电极（505）; 以及设置在第一电极（503）和第二电极（505）之间的电阻变化层（504），电阻变化层的电阻值根据施加在第一电极（503）和第二电极 ）和第二电极（505），其中第一电极和第二电极包括由不同元件制成的材料。

公开(公告)号：US20120280199A1

公开(公告)日：2012-11-08

申请号：US13512178

申请日：2010-11-18

Applicant: Takeshi Takagi

Inventor： Takeshi Takagi

IPC: H01L45/00

CPC classification number: H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1683

Abstract: Provided is a nonvolatile memory element achieving a stable resistance change and miniaturization, and a method of manufacturing the same. The nonvolatile memory element includes: a first electrode formed above a substrate; an interlayer insulating layer formed above the substrate including the first electrode and having a memory cell hole reaching the first electrode; a barrier layer formed in the memory cell hole and composed of a semiconductor layer or an insulating layer connected to the first electrode; a second electrode formed in the memory cell hole and connected to the barrier layer; a variable resistance layer formed on the second electrode and having a stacked structure whose resistance value changes based on electric signals; and a third electrode connected to the variable resistance layer and formed on the interlayer insulating layer to cover the memory cell hole.

Abstract translation: 提供了实现稳定的电阻变化和小型化的非易失性存储元件及其制造方法。 非易失性存储元件包括：形成在衬底上的第一电极; 形成在包括所述第一电极并且具有到达所述第一电极的存储单元孔的所述基板的上方的层间绝缘层; 由存储单元孔形成的阻挡层，由与第一电极连接的半导体层或绝缘层构成; 形成在所述存储单元孔中并连接到所述阻挡层的第二电极; 形成在所述第二电极上并具有电阻值基于电信号而变化的堆叠结构的可变电阻层; 以及连接到所述可变电阻层并形成在所述层间绝缘层上以覆盖所述存储单元孔的第三电极。