发明授权
- 专利标题: Output circuit
- 专利标题(中): 输出电路
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申请号: US10811426申请日: 2004-03-26
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公开(公告)号: US07091789B2公开(公告)日: 2006-08-15
- 发明人: Hideki Shioe
- 申请人: Hideki Shioe
- 申请人地址: JP Osaka
- 专利权人: Sharp Kabushiki Kaisha
- 当前专利权人: Sharp Kabushiki Kaisha
- 当前专利权人地址: JP Osaka
- 代理机构: Morrison & Foerster LLP
- 优先权: JP2003-087813 20030327
- 主分类号: H03F3/04
- IPC分类号: H03F3/04 ; H03F3/45
摘要:
It is an object of the present invention to provide an output circuit capable of reducing a consumption current while an output current is suppressed in a case where limitation is placed on an output voltage so as not to fall to a predetermined voltage or less in an output circuit the emitter of which is grounded, the base of which serves as an input node for a control current and the collector of which serves as an output node. Provided are a base current supply section for supplying a base current to the output transistor according to an input signal from the outside, and a base current control section for detecting an inter-terminal voltage between the collector and emitter of the output transistor to control a base current supplied from the base current supply section so as not to cause the inter-terminal voltage to fall to a value lower than a predetermined voltage.
公开/授权文献
- US20040189401A1 Output circuit 公开/授权日:2004-09-30
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