Invention Grant
- Patent Title: Low voltage non-volatile memory transistor
- Patent Title (中): 低电压非易失性存储晶体管
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Application No.: US11353824Application Date: 2006-02-14
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Publication No.: US07092273B2Publication Date: 2006-08-15
- Inventor: Kevin T. Look
- Applicant: Kevin T. Look
- Applicant Address: US CA San Jose
- Assignee: Xilinx Inc.
- Current Assignee: Xilinx Inc.
- Current Assignee Address: US CA San Jose
- Agent E. Eric Hoffman; Justin Liu
- Main IPC: G11C17/14
- IPC: G11C17/14

Abstract:
A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.
Public/Granted literature
- US20060134839A1 LOW VOLTAGE NON-VOLATILE MEMORY TRANSISTOR Public/Granted day:2006-06-22
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