公开(公告)号：US07092273B2

公开(公告)日：2006-08-15

申请号：US11353824

申请日：2006-02-14

Applicant: Kevin T. Look

Inventor： Kevin T. Look

IPC: G11C17/14

CPC classification number: H01L27/112 ,  H01L27/11206 ,  Y10S257/904

Abstract: A p-channel non-volatile memory (NVM) transistor is programmed by shifting the threshold voltage of the transistor. The threshold voltage is shifted by introducing a programming current to the gate electrode of the transistor, and simultaneously introducing a negative bias to the transistor. The threshold voltage of the p-channel NVM transistor is shifted in response to the negative bias condition and the heat generated by the programming current. The high temperature accelerates the threshold voltage shift. The threshold voltage shift is accompanied by an agglomeration of material in the gate electrode. The agglomeration of material in the gate electrode is an indication of the high temperature reached during programming. The threshold voltage shift of the p-channel NVM transistor is permanent.

Abstract translation: 通过移位晶体管的阈值电压来编程p沟道非易失性存储器（NVM）晶体管。 通过向晶体管的栅电极引入编程电流来移位阈值电压，同时向晶体管引入负偏压。 p沟道NVM晶体管的阈值电压响应于负偏压条件和由编程电流产生的热而偏移。 高温加速阈值电压偏移。 阈值电压偏移伴随着栅电极中材料的聚集。 栅电极中的材料聚集表示编程过程中达到的高温。 p沟道NVM晶体管的阈值电压偏移是永久的。

公开(公告)号：US06936527B1

公开(公告)日：2005-08-30

申请号：US10693467

申请日：2003-10-24

Applicant: Kevin T. Look

Inventor： Kevin T. Look

IPC: G11C16/04 ,  H01L21/336 ,  H01L23/34 ,  H01L23/525 ,  H01L21/22 ,  H01L21/38

CPC classification number: H01L29/66825 ,  G11C16/0408 ,  H01L23/345 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a programming voltage is applied across the metal silicide layer, there is intense localized heating. The heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device. The heating causes carrier activation in the polysilicon layer and dopant penetration through the oxide layer into the channel region, thereby increasing the threshold voltage of the device.

Abstract translation: 存储单元包括在源区和漏区之间的沟道区上形成的多层栅极加热结构。 多层栅极加热结构包括堆叠在类似形状的栅极氧化物上的多晶硅和金属硅化物层。 当跨越金属硅化物层施加编程电压时，存在强烈的局部加热。 加热导致沟道掺杂剂原子朝向源极和漏极区域分离，降低了器件的阈值电压。 加热导致多晶硅层中的载流子活化，并且掺杂剂穿过氧化物层进入沟道区，从而增加器件的阈值电压。

公开(公告)号：US06882571B1

公开(公告)日：2005-04-19

申请号：US10693219

申请日：2003-10-24

Applicant: Kevin T. Look

Inventor： Kevin T. Look

IPC: G11C16/04 ,  H01L21/336 ,  H01L23/34 ,  H01L23/525 ,  G11C7/00

CPC classification number: H01L29/66825 ,  G11C16/0408 ,  H01L23/345 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a programming voltage is applied across the metal silicide layer, there is intense localized heating. The heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device. The heating causes carrier activation in the polysilicon layer and dopant penetration through the oxide layer into the channel region, thereby increasing the threshold voltage of the device.

公开(公告)号：US06563320B1

公开(公告)日：2003-05-13

申请号：US09738815

申请日：2000-12-15

Applicant: Kevin T. Look ,  Shih-Cheng Hsueh

Inventor： Kevin T. Look ,  Shih-Cheng Hsueh

IPC: G01R3108

CPC classification number: G03F7/70633 ,  G01B7/003 ,  H01L22/34

Abstract: An electrical alignment test structure enables monitoring and measuring misalignment between layers (or associated masks) of an IC. The alignment test structure comprises a target region and an alignment feature in different layers. The target region and the alignment feature may be formed in diffusion and polysilicon layers, respectively or in well and diffusion layers, respectively. In both embodiments, the alignment feature controls the size of a conductive channel in the target region. Misalignment can be checked by comparing channel resistance with a baseline (no misalignment) resistance. In another embodiment, the target region and alignment feature are formed in the diffusion and polysilicon layers, respectively, wherein the alignment feature controls the relative widths of the source and drain regions. Misalignment can be checked by comparing current flow with a baseline current. In another embodiment, the target and alignment regions are formed in the well and diffusion layers, respectively, to form a diode, wherein misalignment can be checked by comparing current flow through the alignment feature with a baseline current. Multiple test structures can be combined in an array in accordance with an embodiment of the invention. By configuring the test structures in two mirror-image sets, the array can measure the amount of misalignment between the well and diffusion layers.

公开(公告)号：US06496416B1

公开(公告)日：2002-12-17

申请号：US09742275

申请日：2000-12-19

Applicant: Kevin T. Look

Inventor： Kevin T. Look

IPC: G11C700

CPC classification number: H01L29/66825 ,  G11C16/0408 ,  H01L23/345 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. The gate heating structure includes a fusible portion in the metal silicide layer formed over the channel region. In an unprogrammed state, the memory cell operates as a conventional MOS transistor, with current flow between the source and drain regions being controlled by a control voltage applied to the metal silicide layer. However, when a programming voltage is applied across the metal silicide, layer, the fusible portion agglomerates, generating intense localized heating. In an embodiment of the invention, the memory cell is an NMOS device. Tie heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device. A programmed state is indicated if current flows through the cell even when a logic LOW control voltage is applied. In another embodiment of the invention, the memory cell is a PMOS device having a p-doped polysilicon layer. The heating from agglomeration causes carrier activation in the polysilicon layer and dopant penetration through the oxide layer into the channel region, thereby increasing the threshold voltage of the device. A programmed state is indicated if current flows through the cell even when a logic HIGH control voltage is applied.

Abstract translation: 存储单元包括在源区和漏区之间的沟道区上形成的多层栅极加热结构。 多层栅极加热结构包括堆叠在类似形状的栅极氧化物上的多晶硅和金属硅化物层。 栅极加热结构包括在沟道区域上形成的金属硅化物层中的可熔部分。 在未编程状态下，存储单元作为常规MOS晶体管工作，源极和漏极区域之间的电流流过施加到金属硅化物层的控制电压来控制。 然而，当跨越金属硅化物层施加编程电压时，可熔部分聚集，产生强烈的局部加热。 在本发明的实施例中，存储器单元是NMOS器件。 连接加热导致沟道掺杂剂原子朝向源极和漏极区域分离，降低了器件的阈值电压。 即使当施加逻辑低电平控制电压时，电流也流过单元，则指示编程状态。 在本发明的另一个实施例中，存储单元是具有p掺杂多晶硅层的PMOS器件。 来自聚集的加热导致多晶硅层中的载流子活化，并且掺杂剂穿过氧化物层进入沟道区，从而增加器件的阈值电压。 即使施加了逻辑高电平控制电压，电流也流过单元，指示编程状态。

公开(公告)号：US06465305B1

公开(公告)日：2002-10-15

申请号：US10043962

申请日：2002-01-08

Applicant: Kevin T. Look ,  Shih-Cheng Hsueh

Inventor： Kevin T. Look ,  Shih-Cheng Hsueh

IPC: H01L2980

CPC classification number: H01L22/34

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit. Each structure includes one or more MOS transistors, each of which exhibits a threshold voltage that varies with misalignment in one dimension. The test structures are configured in mirrored pairs, so that misalignment in one direction oppositely affects the threshold voltages of the paired structures. The threshold voltages of the paired structures can therefore be compared to determine the extent and direction of misalignment. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between active implants and the windows in which active regions are formed. Other embodiments measure misalignment between threshold-voltage implants and the active regions.

Abstract translation: 描述了测量集成电路的层之间的未对准的方向和程度的掩模对准检测结构。 每个结构包括一个或多个MOS晶体管，每个MOS晶体管表现出一个维度随着不对准而变化的阈值电压。 测试结构被配置为镜像对，使得一个方向上的未对准相反地影响配对结构的阈值电压。 因此，可以比较成对结构的阈值电压以确定未对准的程度和方向。 根据本发明的测量对于工艺变化相对不敏感，并且用于进行这些测量的结构可以与使用标准工艺的集成电路上的其它特征一起形成。 本发明的一个实施例可用于测量活性植入物与其中形成活性区域的窗口之间的未对准。 其他实施例测量阈值电压植入物和活性区域之间的未对准。

公开(公告)号：US06549458B1

公开(公告)日：2003-04-15

申请号：US10040044

申请日：2001-10-25

Applicant: Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

Inventor： Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

IPC: G11C1400

CPC classification number: G11C16/08

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.

Abstract translation: 用于非易失性存储器件的存储器单元结构和相关电路可以使用标准CMOS工艺制造，例如0.18微米或0.15微米工艺。 有利地，单元结构可以被编程，使得导电路径形成在类型材料之间，例如在p型栅极和p型源极/漏极区域之间或n型栅极和n型源极 /漏区。 以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。

公开(公告)号：US06522582B1

公开(公告)日：2003-02-18

申请号：US09553571

申请日：2000-04-19

Applicant: Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

Inventor： Kameswara K. Rao ,  Martin L. Voogel ,  James Karp ,  Shahin Toutounchi ,  Michael J. Hart ,  Daniel Gitlin ,  Kevin T. Look ,  Jongheon Jeong ,  Radko G. Bankras

IPC: G11C1400

CPC classification number: G11C16/08

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located “on chip” with an array of memory cells. These charge pump circuits are preferably fabricated utilizing the same standard CMOS processing techniques that were utilized to form the memory cell structures and related circuitry.

Abstract translation: 描述了用于非易失性存储器件的存储单元结构和相关电路。 可以使用标准CMOS工艺制造电池结构，例如 次0.35微米或次级0.25微米工艺。 优选地，可以使用0.18微米或0.15微米标准CMOS工艺制造电池结构。 有利地，电池结构可以被编程，使得在相似类型的材料之间形成导电路径。 例如，在某些单元结构中，通过施加编程电压来编程单元，以便在p型栅极和p型源极/漏极区域或n型栅极和n型栅极之间形成导电路径 型源极/漏极区域。 以这种方式编程单元有利地在编程之后提供具有低线性电阻的编程单元。 此外，提供了新颖的电荷泵电路，在优选实施例中，它们以“存储器”阵列位于芯片上。 这些电荷泵电路优选地利用用于形成存储器单元结构和相关电路的相同的标准CMOS处理技术来制造。

公开(公告)号：US5475253A

公开(公告)日：1995-12-12

申请号：US132071

申请日：1993-10-04

Applicant: Kevin T. Look ,  Evert A. Wolsheimer

Inventor： Kevin T. Look ,  Evert A. Wolsheimer

IPC: H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01L27/10 ,  H01L29/04 ,  H01L27/02 ,  H01L49/00

CPC classification number: H01L21/76888 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

Abstract: An antifuse is provided which includes a first conductive layer, an antifuse layer formed on the first conductive layer, and a second conductive layer formed on the antifuse layer. A portion of the antifuse layer forms a substantially orthogonal angle with the first conductive layer and the second conductive layer. This "corner" formation of the antifuse enhances the electric field at this location during programming, thereby providing a predictable location for the filament, i.e. the conductive path between the first and second conductive layers. This antifuse provides other advantages including: a relatively low programming voltage, good step coverage for the antifuse layer and the upper conductive layer, a low, stable resistance value, and minimal shearing effects on the filament.

Abstract translation: 提供一种反熔丝，其包括第一导电层，形成在第一导电层上的反熔丝层，以及形成在反熔丝层上的第二导电层。 反熔丝层的一部分与第一导电层和第二导电层形成大致正交的角度。 反熔丝的这种“角”形成在编程期间增强了该位置处的电场，从而为灯丝提供可预测的位置，即第一和第二导电层之间的导电路径。 该反熔丝提供了其它优点，包括：相对较低的编程电压，反熔丝层和上导电层的良好阶梯覆盖，低稳定的电阻值以及对细丝的最小剪切效应。

公开(公告)号：US07452765B1

公开(公告)日：2008-11-18

申请号：US11242409

申请日：2005-09-30

Applicant: Martin L. Voogel ,  Austin H. Lesea ,  Joseph J. Fabula ,  Carl H. Carmichael ,  Shahin Toutounchi ,  Michael J. Hart ,  Steven P. Young ,  Kevin T. Look ,  Jan L. de Jong

Inventor： Martin L. Voogel ,  Austin H. Lesea ,  Joseph J. Fabula ,  Carl H. Carmichael ,  Shahin Toutounchi ,  Michael J. Hart ,  Steven P. Young ,  Kevin T. Look ,  Jan L. de Jong

IPC: H01L21/8238

CPC classification number: H01L27/11803 ,  H01L21/76831 ,  H01L21/76834 ,  H01L27/11

Abstract: SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.

Abstract translation: SEU硬化串联电阻负载形成在锁存器的交叉耦合反相器的栅极结构内。 对于一些实施例，用于每个交叉耦合的反相器的输入的栅极接触具有足够高的电阻以提供SEU-硬化串联电阻。 对于其他实施例，耦合到每个交叉耦合的反相器的输入的导电迹线层包括提供SEU硬化串联电阻的高电阻部分。