发明授权
US07099201B1 Multifunctional latch circuit for use with both SRAM array and self test device
失效
多功能锁存电路,用于SRAM阵列和自检装置
- 专利标题: Multifunctional latch circuit for use with both SRAM array and self test device
- 专利标题(中): 多功能锁存电路,用于SRAM阵列和自检装置
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申请号: US11055043申请日: 2005-02-10
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公开(公告)号: US07099201B1公开(公告)日: 2006-08-29
- 发明人: Andrew James Bianchi , Yuen Hung Chan , William Vincent Huott , Michael Ju Hyeok Lee , Edelmar Seewann , Philip George Shephard, III
- 申请人: Andrew James Bianchi , Yuen Hung Chan , William Vincent Huott , Michael Ju Hyeok Lee , Edelmar Seewann , Philip George Shephard, III
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Duke W. Yee; Mark E. McBurney; James O. Starstein
- 主分类号: G11C7/10
- IPC分类号: G11C7/10
摘要:
An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode.
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