利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

6 条记录 (耗时 0.047 秒)

    Multifunctional latch circuit for use with both SRAM array and self test device
    1.
    发明授权
    Multifunctional latch circuit for use with both SRAM array and self test device 失效
    多功能锁存电路，用于SRAM阵列和自检装置

    公开(公告)号：US07099201B1

    公开(公告)日：2006-08-29

    申请号：US11055043

    申请日：2005-02-10

    申请人： Andrew James Bianchi ,  Yuen Hung Chan ,  William Vincent Huott ,  Michael Ju Hyeok Lee ,  Edelmar Seewann ,  Philip George Shephard, III

    发明人： Andrew James Bianchi ,  Yuen Hung Chan ,  William Vincent Huott ,  Michael Ju Hyeok Lee ,  Edelmar Seewann ,  Philip George Shephard, III

    IPC分类号： G11C7/10

    CPC分类号： G11C29/1201 ,  G11C11/41 ,  G11C11/419 ,  G11C29/12

    摘要： An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode.

    摘要翻译： 提供了一种在单个锁存电路中组合自检和功能特征的装置和方法，其可以与SRAM阵列一起使用，并且被有效地实现为L1-L2锁存器。 在从SRAM阵列的部分写入期间，未知状态的数据位被禁止进入锁存电路，而用于测试的数据被允许进入。 在本发明的一个有用的实施例中，锁存电路与提供模式选择信号的模式控制一起使用，以便以至少全写和部分写模式的多种模式之一来操作锁存电路。 锁存电路还包括数据保持电路，用于选择性地接收和存储耦合到锁存电路的数据。 响应于模式选择信号的第一使能电路使得保持电路能够在完全写入模式期间接收包含在阵列中的所有数据，并且还允许保持电路仅在部分时钟期间仅接收阵列中包含的一些数据位 写模式。

    Apparatus and method for detecting multiple hits in CAM arrays
    3.
    发明授权
    Apparatus and method for detecting multiple hits in CAM arrays 失效

    公开(公告)号：US07092270B2

    公开(公告)日：2006-08-15

    申请号：US10880719

    申请日：2004-06-30

    申请人： Michael Ju Hyeok Lee ,  Sheldon B. Levenstein ,  Edelmar Seewann

    发明人： Michael Ju Hyeok Lee ,  Sheldon B. Levenstein ,  Edelmar Seewann

    IPC分类号： G11C15/00

    CPC分类号： G11C15/00

    摘要： An apparatus and method are disclosed for detecting multiple hits in CAM arrays. A binary address value is stored for each entry of the CAM array and is output to identify the matching entry for a single hit. However, to facilitate multiple hit detection, both the true and complement components of this address are stored and output to determine whether or not a multiple hit occurred. If a multiple hit occurs (e.g., more than one address location has been matched), all the bits that make up the binary address and the complement will not be complements of each other and a multiple hit condition can be detected by XORing each bit of an address location value with the complement of that address location value. If the XORed bits are equal to “1”, then a single hit has occurred. Otherwise, a multiple hit has occurred.

    MULTIFUNCTIONAL LATCH CIRCUIT FOR USE WITH BOTH SRAM ARRAY AND SELF TEST DEVICE
    4.
    发明申请
    MULTIFUNCTIONAL LATCH CIRCUIT FOR USE WITH BOTH SRAM ARRAY AND SELF TEST DEVICE 失效
    具有两个SRAM阵列和自检测试器件的多功能锁存电路

    公开(公告)号：US20060176731A1

    公开(公告)日：2006-08-10

    申请号：US11055043

    申请日：2005-02-10

    申请人： Andrew Bianchi ,  Yuen Chan ,  William Huott ,  Michael Hyeok Lee ,  Edelmar Seewann ,  Philip Shephard

    发明人： Andrew Bianchi ,  Yuen Chan ,  William Huott ,  Michael Hyeok Lee ,  Edelmar Seewann ,  Philip Shephard

    IPC分类号： G11C11/00

    CPC分类号： G11C29/1201 ,  G11C11/41 ,  G11C11/419 ,  G11C29/12

    摘要： An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode, while preventing other data bits of “X” state from entering the latch circuit. A second enabling circuit enables the data hold circuit to receive data bits from a self test source in place of respective data bits from the SRAM array that are prevented from entering the latch circuit.

    摘要翻译： 提供了将单个锁存电路中的自检和功能特征组合在一起的装置和方法，其可以与SRAM阵列一起使用，并且被有效地实现为L 1 -L 2锁存器。 在从SRAM阵列的部分写入期间，未知状态的数据位被禁止进入锁存电路，而用于测试的数据被允许进入。 在本发明的一个有用的实施例中，锁存电路与提供模式选择信号的模式控制一起使用，以便以至少全写和部分写模式的多种模式之一来操作锁存电路。 锁存电路还包括数据保持电路，用于选择性地接收和存储耦合到锁存电路的数据。 响应于模式选择信号的第一使能电路使得保持电路能够在完全写入模式期间接收包含在阵列中的所有数据，并且还允许保持电路仅在部分时钟期间仅接收阵列中包含的一些数据位 写模式，同时防止“X”状态的其他数据位进入锁存电路。 第二启用电路使得数据保持电路能够从自检源代替来自SRAM阵列的相应数据位，以防止其进入锁存电路。

    Apparatus and method for detecting multiple hits in CAM arrays
    5.
    发明申请
    Apparatus and method for detecting multiple hits in CAM arrays 失效
    用于检测CAM阵列中多次命中的装置和方法

    公开(公告)号：US20060002163A1

    公开(公告)日：2006-01-05

    申请号：US10880719

    申请日：2004-06-30

    申请人： Michael Ju Lee ,  Sheldon Levenstein ,  Edelmar Seewann

    发明人： Michael Ju Lee ,  Sheldon Levenstein ,  Edelmar Seewann

    IPC分类号： G11C15/00

    CPC分类号： G11C15/00

    摘要： An apparatus and method are disclosed for detecting multiple hits in CAM arrays. A binary address value is stored for each entry of the CAM array and is output to identify the matching entry for a single hit. However, to facilitate multiple hit detection, both the true and complement components of this address are stored and output to determine whether or not a multiple hit occurred. If a multiple hit occurs (e.g., more than one address location has been matched), all the bits that make up the binary address and the complement will not be complements of each other and a multiple hit condition can be detected by XORing each bit of an address location value with the complement of that address location value. If the XORed bits are equal to “1”, then a single hit has occurred. Otherwise, a multiple hit has occurred.

    摘要翻译： 公开了用于检测CAM阵列中的多个命中的装置和方法。 为CAM阵列的每个条目存储二进制地址值，并输出以识别单个命中的匹配条目。 然而，为了便于多次命中检测，存储和输出该地址的真实和补码成分，以确定是否发生多次命中。 如果发生多重命中（例如，多于一个地址位置已匹配），构成二进制地址和补码的所有位将不会互相补充，并且可以通过将每个位的异或来检测多个命中条件 具有该地址位置值的补码的地址位置值。 如果异或位等于“1”，则发生单击。 否则，发生多重命中。