The present invention facilitates more accurate data reads by compensating for parasitic behavior—thus regulating the voltage at the drain of a core memory cell rather than at the output of a sensing circuit. More particularly, respective voltages at one or more nodes, such as the start of a bitline at a sensing circuit, for example, are adjusted to compensate for voltage drops that may occur due to parasitic behavior. Maintaining the substantially constant voltage levels at core memory cells allows comparisons to be made under ideal conditions while reducing the side leakages in virtual ground schemes. This mitigates margin loss and facilitates more reliable data sensing.