A DAC (1) has a switched element capacitor (7, Cr) to which charge is delivered via switches (6, S1/S2) depending on required analog voltage level (Vref1, Vref2). An output switch (S3) is closed and a ground switch (S4) is opened to deliver charge to the output according to received bi-level digital inputs (+1, −1). The control block (2) has a memory and determines an inactive output level if there is an input digital transition from +1 to −1 or from −1 to +1. For the inactive level S3 is kept open and S4 is kept closed. Thus, for every clock cycle with one of these transitions there is no charge transfer and hence no thermal noise. Overall noise is therefore considerably reduced.