公开(公告)号：US20160094240A1

公开(公告)日：2016-03-31

申请号：US14496980

申请日：2014-09-25

Applicant: Anthony Evan O'Shaughnessy ,  Colin Lyden ,  Joseph Peter Canning

Inventor： Anthony Evan O'Shaughnessy ,  Colin Lyden ,  Joseph Peter Canning

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03H17/0621 ,  H03H17/0642 ,  H03H17/0664 ,  H03H17/0685

Abstract: It is known to perform sample rate conversion. A sample rate converter is arranged to receive digital data at an input sample rate Fs and to output data at an output sample rate Fo, where Fo=Fs/N, and N is decimation factor greater than 1. A problem can arise with sample rate converters when a user wishes to change the decimation rate. Generally a sample rate converter needs to discard the samples in its filter when the decimation rate is changed, and the filter output is unusable until the filter has refilled with values taken at the new decimation rate. The sample rate converter provided here does not suffer from this problem. The sample rate converter includes at least Q channels. Each channel comprises a Qth order filter arranged to select input signals at predetermined intervals from a run of P input signals, and to form a weighted sum of the selected input signals to generate an output value, and where the runs of P input signals of one channel are offset from the runs of P signals of the other channels.

Abstract translation: 已知进行采样率转换。 采样率转换器被布置为以输入采样率Fs接收数字数据，并以输出采样率Fo输出数据，其中Fo = Fs / N，N是抽取因子大于1.可能会出现采样率的问题 转换器，当用户希望改变抽取率时。 通常，抽样速率改变时，采样率转换器需要丢弃其滤波器中的样本，并且滤波器输出不可用，直到滤波器用新的抽取率取值为止。 这里提供的采样率转换器不会受到这个问题的困扰。 采样率转换器至少包括Q个通道。 每个通道包括Q阶滤波器，其布置成从P个输入信号的行程中以预定间隔选择输入信号，并且形成所选输入信号的加权和以产生输出值，并且其中一个P输入信号的运行 通道偏离其他通道的P信号的运行。

公开(公告)号：US20140132325A1

公开(公告)日：2014-05-15

申请号：US14158416

申请日：2014-01-17

Applicant: Colin LYDEN ,  Donal BOURKE ,  Dennis A. DEMPSEY ,  Dermot G. O'KEEFFE ,  Patrick KIRBY

Inventor： Colin LYDEN ,  Donal BOURKE ,  Dennis A. DEMPSEY ,  Dermot G. O'KEEFFE ,  Patrick KIRBY

IPC: H03L5/00

CPC classification number: G01N27/028 ,  G01N27/3273 ,  G01N27/49 ,  H03F1/34 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2200/462 ,  H03L5/00

Abstract: A control circuit for use with a four terminal sensor, the sensor having first and second drive terminals and first and second measurement terminals, the control circuit arranged to drive at least one of the first and second drive terminals with an excitation signal, to sense a voltage difference between the first and second measurement terminals, and control the excitation signal such that the voltage difference between the first and second measurement terminals is within a target range of voltages, and wherein the control circuit includes N poles in its transfer characteristic and N−1 zeros in its transfer characteristic such that when a loop gain falls to unity the phase shift around a closed loop is not substantially 2π radians or a multiple thereof, where N is greater than 1.

Abstract translation: 一种与四端子传感器一起使用的控制电路，所述传感器具有第一和第二驱动端子以及第一和第二测量端子，所述控制电路被布置成用激励信号驱动第一和第二驱动端子中的至少一个，以感测 并且控制所述激励信号，使得所述第一测量端子与所述第二测量端子之间的电压差在目标电压范围内，并且其中所述控制电路在其传输特性中包括N极，并且所述N- 1个零的传递特性使得当环路增益下降到1时，围绕闭环的相移基本上不是2＆pgr; 弧度或其倍数，其中N大于1。

公开(公告)号：US08659349B1

公开(公告)日：2014-02-25

申请号：US13626630

申请日：2012-09-25

Applicant: Colin Lyden ,  Donal Bourke ,  Dennis A. Dempsey ,  Dermot G. O'Keeffe ,  Patrick Kirby

Inventor： Colin Lyden ,  Donal Bourke ,  Dennis A. Dempsey ,  Dermot G. O'Keeffe ,  Patrick Kirby

IPC: G06G7/12

CPC classification number: G01N27/028 ,  G01N27/3273 ,  G01N27/49 ,  H03F1/34 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2200/462 ,  H03L5/00

Abstract: A control circuit for use with a four terminal sensor, the sensor having first and second drive terminals and first and second measurement terminals, the control circuit arranged to drive at least one of the first and second drive terminals with an excitation signal, to sense a voltage difference between the first and second measurement terminals, and control the excitation signal such that the voltage difference between the first and second measurement terminals is within a target range of voltages, and wherein the control circuit includes N poles in its transfer characteristic and N−1 zeros in its transfer characteristic such that when a loop gain falls to unity the phase shift around a closed loop is not substantially 2π radians or a multiple thereof, where N is greater than 1.

Abstract translation: 一种与四端子传感器一起使用的控制电路，所述传感器具有第一和第二驱动端子以及第一和第二测量端子，所述控制电路被布置成用激励信号驱动第一和第二驱动端子中的至少一个，以感测 并且控制所述激励信号，使得所述第一测量端子与所述第二测量端子之间的电压差在目标电压范围内，并且其中所述控制电路在其传输特性中包括N极，并且所述N- 1的零传递特性使得当环路增益下降到1时，围绕闭环的相移基本上不是2pi弧度或其倍数，其中N大于1。

公开(公告)号：US20120256578A1

公开(公告)日：2012-10-11

申请号：US13529923

申请日：2012-06-21

Applicant: Colin LYDEN ,  Javier CALPE-MARAVILLA ,  Mark MURPHY ,  Eoin ENGLISH ,  Denis Martin O'CONNOR

Inventor： Colin LYDEN ,  Javier CALPE-MARAVILLA ,  Mark MURPHY ,  Eoin ENGLISH ,  Denis Martin O'CONNOR

IPC: G05B11/36

CPC classification number: H02P23/0077

Abstract: A drive signal for a motor-driven mechanical system has zero (or near zero) energy at an expected resonant frequency of the mechanical system. These techniques not only generate a drive signal with substantially no energy at the expected resonant frequency, they provide a zero-energy “notch” of sufficient width to tolerate systems in which the actual resonant frequency differs from the expected resonant frequencies.

Abstract translation: 在机械系统的预期谐振频率下，用于电动机械系统的驱动信号具有零（或接近于零）的能量。 这些技术不仅在预期谐振频率下产生基本上没有能量的驱动信号，它们提供足够宽度的零能量陷波，以容忍其中实际谐振频率与预期谐振频率不同的系统。

公开(公告)号：US08040264B2

公开(公告)日：2011-10-18

申请号：US12717448

申请日：2010-03-04

Applicant: Derek Hummerston ,  Christopher Peter Hurrell ,  Colin Lyden

Inventor： Derek Hummerston ,  Christopher Peter Hurrell ,  Colin Lyden

IPC: H03M1/06

CPC classification number: H03M1/12

Abstract: A pipeline analog to digital converter comprising: a first analog to digital converter for determining a first part of an analog to digital conversion result, and for forming a residue signal; an amplifier for amplifying the residue signal, the amplifier including at least one offset sampling capacitor for sampling an offset of the amplifier, wherein at least one resistance is associated with the at least one capacitor so as to form a filter, and the at least one resistor is variable such that an amplifier bandwidth can be switched between a first bandwidth and a second bandwidth less than the first bandwidth during sampling of the offset.

Abstract translation: 一种管线模数转换器，包括：第一模数转换器，用于确定模数转换结果的第一部分，以及用于形成残留信号; 用于放大残留信号的放大器，所述放大器包括用于对放大器的偏移进行采样的至少一个偏移采样电容器，其中至少一个电阻与所述至少一个电容器相关联以形成滤波器，并且所述至少一个 电阻器是可变的，使得在偏移的采样期间，可以在第一带宽和小于第一带宽的第二带宽之间切换放大器带宽。

公开(公告)号：US20100201301A1

公开(公告)日：2010-08-12

申请号：US12367883

申请日：2009-02-09

Applicant: Colin LYDEN ,  Javier CALPE-MARAVILLA ,  Mark MURPHY ,  Eoin ENGLISH

Inventor： Colin LYDEN ,  Javier CALPE-MARAVILLA ,  Mark MURPHY ,  Eoin ENGLISH

IPC: G05B11/26

CPC classification number: H02P25/034

Abstract: Embodiments of the present invention provide a drive signal for a motor-driven mechanical system whose frequency distribution has zero (or near zero) energy at the expected resonant frequency of the mechanical system. The drive signal may be provided as a pair of steps sufficient to activate movement of the mechanical system and then park the mechanical system at a destination position. The steps are spaced in time so as to have substantially zero energy at an expected resonant frequency fR of the mechanical system. The drive signal may be filtered to broaden a zero-energy notch at the expected resonant frequency fR.

Abstract translation: 本发明的实施例提供了一种用于机械系统的预期谐振频率的频率分布具有零（或接近零）能量的电机驱动机械系统的驱动信号。 驱动信号可以被提供为足以激活机械系统的运动并随后将机械系统停放在目的地位置的一对步骤。 这些步骤在时间上间隔开，以便在机械系统的预期谐振频率fR处具有基本上零的能量。 可以对驱动信号进行滤波，以便以预期的谐振频率fR扩大零能量陷波。

公开(公告)号：US20090140897A1

公开(公告)日：2009-06-04

申请号：US11998618

申请日：2007-11-30

Applicant: John Healy ,  Colin Lyden

Inventor： John Healy ,  Colin Lyden

IPC: H03M1/06

CPC classification number: H03M3/484 ,  H03M3/338 ,  H03M3/434

Abstract: A gain matching method for a single bit gain ranging analog to digital converter including selecting, in response to a gain setting, a number of gain elements to be enabled in a multi-element gain controlled array interconnected between an analog input and an analog to digital converter, and patterning the enablement of the selected number of gain elements among the gain elements for matching the gain of the analog to digital converter for a range of gain settings of the converter to reduce in-band gain error due to gain element mismatch.

Abstract translation: 一种用于单位增益测距模数转换器的增益匹配方法，包括响应于增益设置，选择在模拟输入和模数转换器之间互连的多元件增益控制阵列中使能的增益元件数量 转换器，并且在增益元件中对选定数量的增益元件的启用进行构图，以便在转换器的增益设置的范围内匹配模数转换器的增益，以减少由于增益元件失配引起的带内增益误差。

公开(公告)号：US20070109067A1

公开(公告)日：2007-05-17

申请号：US11494345

申请日：2006-07-27

Applicant: Cormac O'Sullivan ,  Colin Lyden ,  Hyman Shanan

Inventor： Cormac O'Sullivan ,  Colin Lyden ,  Hyman Shanan

IPC: H03C3/09

CPC classification number: H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0991 ,  H03L7/1976

Abstract: A phase lock loop RF modulator system including a phase lock loop circuit having a phase detector circuit responsive to an input reference signal and a feedback signal, an oscillator circuit responsive to the phase detector circuit for providing an output signal, a forward path from the phase detector circuit to the oscillator circuit, and a feedback path from the oscillator circuit to the phase detector circuit. The system also includes a first modulation port coupled to the feedback path, a second modulation port coupled to the forward path, and a gain mismatch detection circuit responsive to modulation data and a phase error between the reference signal and the feedback signal for providing an indicator output signal that represents the gain mismatch between the first modulation port and the second modulation port.

Abstract translation: 一种锁相环RF调制器系统，包括一个锁相环电路，该电路具有响应于输入参考信号和反馈信号的相位检测器电路，响应相位检测器电路提供输出信号的振荡器电路，从相位 检测器电路到振荡器电路，以及从振荡器电路到相位检测器电路的反馈路径。 该系统还包括耦合到反馈路径的第一调制端口，耦合到正向通路的第二调制端口，以及响应于调制数据的增益失配检测电路和参考信号与反馈信号之间的相位误差，用于提供指示器 输出信号，其表示第一调制端口和第二调制端口之间的增益失配。

公开(公告)号：US20060250291A1

公开(公告)日：2006-11-09

申请号：US11122587

申请日：2005-05-05

Applicant: Colin Lyden ,  Michael Coln ,  Robert Brewer

Inventor： Colin Lyden ,  Michael Coln ,  Robert Brewer

IPC: H03M1/12

CPC classification number: H03M1/08 ,  H03M1/122

Abstract: An accurate, low noise conditionally resetting integrator circuit in an analog to digital system samples, with an analog to digital converter, the output of an integrating circuit a number of times during a measuring period; isolates the input for the integrating circuit during sample event; generates a reset signal in response to the integrating circuit output reaching a predetermined level; and resets the feedback capacitor of the integrating circuit by isolating it from the amplifier circuit of the integrating circuit and connecting it to a reference source during a sample event.

Abstract translation: 模拟数字系统中的精确低噪声有条件复位积分电路采样模数转换器，在测量期间多次输出积分电路; 在采样事件期间隔离积分电路的输入; 响应于所述积分电路输出达到预定水平而产生复位信号; 并且通过将其与积分电路的放大器电路隔离并且在采样事件期间将其连接到参考源来复位积分电路的反馈电容器。

公开(公告)号：US20060139192A1

公开(公告)日：2006-06-29

申请号：US11228113

申请日：2005-09-16

Applicant: Paul Morrow ,  Maria del Mar Chamarro Marti ,  Colin Lyden ,  Mike Keane ,  Robert Adams ,  Richard O'Brien ,  Paschal Minogue ,  Hans Mansson

Inventor： Paul Morrow ,  Maria del Mar Chamarro Marti ,  Colin Lyden ,  Mike Keane ,  Robert Adams ,  Richard O'Brien ,  Paschal Minogue ,  Hans Mansson

IPC: H03M3/00

CPC classification number: H03M3/34 ,  H03M3/332 ,  H03M3/424 ,  H03M3/454

Abstract: A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has a differential input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a digital feedback signal from a flash ADC. An integrator has a differential input that integrates the difference of the generated current by the multi-bit IDAC and the input signal current on a continuous-time basis. The input stage further comprises a first biasing current source and a second biasing current source which bias the input stage in a mid-scale condition. A first summing node connects to the first differential input line, a first differential input of the integrator and the first output branch. A second summing node connects to the second differential input line, a second differential input of the integrator and the second output branch. A set of chopping switches alternately connect the biasing current sources to the summing nodes in a first configuration and a second, reversed, configuration. The converter receives a modulator clock signal at a frequency FS and the chopping switches can operate at FS or a binary subdivision thereof. The integrator amplifier can also be chopper-stabilized.

Abstract translation: 多位连续时间Σ-Δ模数转换器（ADC）具有接收模拟输入信号电流的差分输入级。 多位反馈电流数模转换器（IDAC）根据闪存ADC的数字反馈信号产生多电平反馈电流。 积分器具有差分输入，其通过多位IDAC产生的电流与输入信号电流的连续时间积分。 输入级还包括第一偏置电流源和在中等尺度条件下偏置输入级的第二偏置电流源。 第一求和节点连接到第一差分输入线，积分器的第一差分输入和第一输出分支。 第二求和节点连接到第二差分输入线，积分器和第二输出分支的第二差分输入。 一组斩波开关将偏置电流源以第一配置和第二反向配置交替地连接到求和节点。 转换器以频率F S S接收调制器时钟信号，并且斩波开关可以在F S或其二进制细分上工作。 积分放大器也可以斩波稳定。