发明授权
- 专利标题： Method of partitioning an integrated circuit design for physical design verification
- 专利标题（中）： 分离用于物理设计验证的集成电路设计的方法
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申请号： US10697357申请日： 2003-10-29
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公开(公告)号： US07107559B2公开(公告)日： 2006-09-12
- 发明人: Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
- 申请人： Viswanathan Lakshmanan , Richard D. Blinne , Jonathan P. Kuppinger
- 申请人地址： US CA Milpitas
- 专利权人： LSI Logic Corporation
- 当前专利权人： LSI Logic Corporation
- 当前专利权人地址： US CA Milpitas
- 代理商 Eric J. Whitsell
- 主分类号： G06F17/50
- IPC分类号： G06F17/50 ; G06F9/45
摘要：
A method of partitioning an integrated circuit design for physical design verification includes steps of receiving as input a representation of an integrated circuit design having a number of physical design layers and a composite run deck specifying rule checks to be performed on the integrated circuit design. The composite run deck is partitioned into partitioned run decks so that the number of physical design layers referenced by each of the partitioned run decks is a minimum. The representation of the integrated circuit design is parsed to filter only the physical design layers required for each of the partitioned run decks into a filtered data deck for each of the partitioned run decks. The filtered data deck is generated as output for each of the partitioned run decks.
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