Invention Grant
- Patent Title: Sealing structure with barrier membrane for electronic element, display device, electronic apparatus, and fabrication method for electronic element
- Patent Title (中): 用于电子元件的屏障膜的密封结构,显示装置,电子设备和电子元件的制造方法
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Application No.: US10341400Application Date: 2003-01-14
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Publication No.: US07109653B2Publication Date: 2006-09-19
- Inventor: Yoichi Imamura
- Applicant: Yoichi Imamura
- Applicant Address: JP Tokyo
- Assignee: Seiko Epson Corporation
- Current Assignee: Seiko Epson Corporation
- Current Assignee Address: JP Tokyo
- Agency: Oliff & Berridge, PLC
- Priority: JP2002-006572 20020115
- Main IPC: H05B33/04
- IPC: H05B33/04

Abstract:
A sealing structure having a barrier membrane, with which the overall thickness of a display device can be reduced while ensuring sufficient barrier properties against water and oxygen so as to prevent deterioration of luminous layers. The sealing structure includes a multi-layered resin membrane for sealing an electronic element section disposed on a substrate, which is formed by alternately depositing flattening resin layers and barrier layers on the substrate. The flattening resin layers are formed inside a blocking region surrounding the electronic element section. A display device having the sealing structure, an electronic apparatus having the display device, and a fabrication method for the display device are also disclosed.
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