A synchronous clock phase control circuit includes a T/8 step phase clock generation unit, a phase selection unit, and four synchronous clock generation units. The T/8 step phase clock generation unit generates eight clocks previously delayed in phase by T/8 from an input clock. The phase selection unit selects four control clocks from the eight clocks generated by the phase clock generation unit based on four phase control signals, respectively. The four synchronous clock generation units synchronize the selected clocks with an externally input trigger signal TR using the input clock as a reference, and output the selected clocks when synchronization is established, respectively.