发明授权
US07124252B1 Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system
有权
用于将有序输入/输出事务流水线分配存储器，高速缓存一致的多处理器系统中的相干存储器的方法和装置
- 专利标题： Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system
- 专利标题（中）： 用于将有序输入/输出事务流水线分配存储器，高速缓存一致的多处理器系统中的相干存储器的方法和装置
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申请号： US09643380申请日： 2000-08-21
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公开(公告)号： US07124252B1公开(公告)日： 2006-10-17
- 发明人: Manoj Khare , Akhilesh Kumar , Lily P. Looi , Kenneth C. Creta
- 申请人： Manoj Khare , Akhilesh Kumar , Lily P. Looi , Kenneth C. Creta
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理商 Cynthia Thomas Faatz
- 主分类号： G06F13/14
- IPC分类号： G06F13/14
摘要：
An approach for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system. A prefetch engine prefetches data from the distributed, coherent memory in response to a transaction from an input/output bus directed to the distributed, coherent memory. An input/output coherent cache buffer receives the prefetched data and is kept coherent with the distributed, coherent memory and with other caching agents in the system.