发明授权
- 专利标题: Logic simulation
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申请号: US09942116申请日: 2001-08-29
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公开(公告)号: US07130784B2公开(公告)日: 2006-10-31
- 发明人: William R. Wheeler , Timothy J. Fennell , Matthew J. Adiletta
- 申请人: William R. Wheeler , Timothy J. Fennell , Matthew J. Adiletta
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Fish & Richardson P.C.
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
Logic simulation includes storing a first state to identify in a simulation of a logic design whether a node included in the logic design has a logic high value Logic simulation also includes storing a second state to identify in simulation of the logic design whether the node has a logic low value and storing a third state to identify in simulation of the logic design whether the node has an undefined state. The logic simulation determines an output of the node in simulation of the logic design based on the first state, the second state, and the third state.
公开/授权文献
- US20030046053A1 Logic simulation 公开/授权日:2003-03-06
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