发明授权
US07144764B2 Method of manufacturing semiconductor device having trench isolation
失效
制造具有沟槽隔离的半导体器件的方法
- 专利标题： Method of manufacturing semiconductor device having trench isolation
- 专利标题（中）： 制造具有沟槽隔离的半导体器件的方法
-
申请号： US10949451申请日： 2004-09-27
-
公开(公告)号： US07144764B2公开(公告)日： 2006-12-05
- 发明人: Takuji Matsumoto , Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Shigeto Maegawa
- 申请人： Takuji Matsumoto , Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Shigeto Maegawa
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
- 优先权： JP2002-036563 20020214
- 主分类号： H01L21/762
- IPC分类号： H01L21/762
摘要：
The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).
公开/授权文献
信息查询
IPC分类:
