发明授权
US07145829B1 Single cycle refresh of multi-port dynamic random access memory (DRAM)
有权
多端口动态随机存取存储器（DRAM）的单周期刷新
- 专利标题： Single cycle refresh of multi-port dynamic random access memory (DRAM)
- 专利标题（中）： 多端口动态随机存取存储器（DRAM）的单周期刷新
-
申请号： US11160273申请日： 2005-06-16
-
公开(公告)号： US07145829B1公开(公告)日： 2006-12-05
- 发明人: Hoki Kim , Toshiaki Kirihata
- 申请人： Hoki Kim , Toshiaki Kirihata
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理商 Lisa U. Jaklitsch
- 主分类号： C11C7/00
- IPC分类号： C11C7/00
摘要：
A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.
公开/授权文献
信息查询
