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    SINGLE CYCLE REFRESH OF MULTI-PORT DYNAMIC RANDOM ACCESS MEMORY (DRAM)
    1.
    发明申请
    SINGLE CYCLE REFRESH OF MULTI-PORT DYNAMIC RANDOM ACCESS MEMORY (DRAM) 有权
    多端口动态随机存取存储器（DRAM）的单周期刷新

    公开(公告)号：US20060285411A1

    公开(公告)日：2006-12-21

    申请号：US11160273

    申请日：2005-06-16

    申请人： Hoki Kim ,  Toshiaki Kirihata

    发明人： Hoki Kim ,  Toshiaki Kirihata

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4097 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4094

    摘要： A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.

    摘要翻译： 具有与正常读取和写入操作交织的刷新周期的多端口DRAM通过推迟序列的写入部分直到下一个刷新周期来实现单周期刷新序列。 在单个时钟周期内，系统将存储的数据从刷新缓冲区写入存储器阵列中的一行，然后将数据从存储器阵列的一行读入缓冲区。

    Single cycle refresh of multi-port dynamic random access memory (DRAM)
    2.
    发明授权
    Single cycle refresh of multi-port dynamic random access memory (DRAM) 有权
    多端口动态随机存取存储器（DRAM）的单周期刷新

    公开(公告)号：US07145829B1

    公开(公告)日：2006-12-05

    申请号：US11160273

    申请日：2005-06-16

    申请人： Hoki Kim ,  Toshiaki Kirihata

    发明人： Hoki Kim ,  Toshiaki Kirihata

    IPC分类号： C11C7/00

    CPC分类号： G11C11/4097 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4094

    摘要： A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.

    摘要翻译： 具有与正常读取和写入操作交错的刷新周期的多端口DRAM通过推迟序列的写入部分直到下一个刷新周期来实现单周期刷新序列。 在单个时钟周期内，系统将存储的数据从刷新缓冲区写入存储器阵列中的一行，然后将数据从存储器阵列的一行读入缓冲区。

    Three Dimensional Twisted Bitline Architecture for Multi-port Memory
    3.
    发明申请
    Three Dimensional Twisted Bitline Architecture for Multi-port Memory 失效
    用于多端口存储器的三维扭转位线架构

    公开(公告)号：US20090103390A1

    公开(公告)日：2009-04-23

    申请号：US11875173

    申请日：2007-10-19

    申请人： Hoki Kim ,  Toshiaki Kirihata

    发明人： Hoki Kim ,  Toshiaki Kirihata

    IPC分类号： G11C8/00

    CPC分类号： G11C8/16 ,  G11C7/02 ,  G11C7/1075 ,  G11C7/18 ,  G11C11/412

    摘要： Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.

    摘要翻译： 本发明的实施例提供了双重部分单元的存储器阵列及其设计结构。 存储器阵列具有一对扭曲的写位线和用于每列的一对扭转的读位线。 通过在列的每个部分中交替每个位线对的垂直位置来进行扭转，从而产生共模鼻子并且减小差模噪声。

    Multi-port memory architecture
    6.
    发明授权
    Multi-port memory architecture 有权
    多端口内存架构

    公开(公告)号：US06990025B2

    公开(公告)日：2006-01-24

    申请号：US10604994

    申请日：2003-08-29

    申请人： Toshiaki Kirihata ,  Hoki Kim ,  Matthew Wordeman

    发明人： Toshiaki Kirihata ,  Hoki Kim ,  Matthew Wordeman

    IPC分类号： G11C7/00

    CPC分类号： G11C11/405 ,  G11C8/16 ,  G11C11/4099

    摘要： A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors. For a given sense amplifier and its associated RBLs, the coupling creates an identical coupling noise on RBLA and RBLB that are positioned in the two arrays A and B. This common mode noise is rejected by the differential sense amplifier. Thus, a read sense amplifier can accurately discriminate between the signal by activating the cell by way of RWL, and the reference cell by way of REFWL.

    摘要翻译： 描述了利用读取位线的开放位线配置的多端口存储器架构。 存储器被细分为由矩阵形式排列的存储器增益单元组成的两个阵列（A和B），这些单元具有两个通用端口或单独的读取和写入端口，以实现读写操作。 每个存储器阵列包括耦合到参考单元的参考字线。 当参考单元被访问时，读位线（RBL）放电到由存储0或1的单元取得的值的一半的电平上。两个阵列的同一列中的每对RBLB耦合到差分读出放大器 ，并且两个阵列中的每个写入位线（WBL）链接到写入驱动器，两个阵列中的WBLs被驱动到相同的电压和相同的转换速率。 每个阵列中的WBL摆幅通过位线到位线电容产生耦合噪声。 对于给定的读出放大器及其相关联的RBL，耦合在位于两个阵列A和B中的RBLA和RBLB上产生相同的耦合噪声。这种共模噪声被差分读出放大器拒绝。 因此，读出读出放大器可以通过RWL通过激活单元以及通过REFWL来使参考单元精确地区分信号。

    MULTI-PORT MEMORY ARCHITECTURE
    7.
    发明申请
    MULTI-PORT MEMORY ARCHITECTURE 有权
    多端口存储器架构

    公开(公告)号：US20050047218A1

    公开(公告)日：2005-03-03

    申请号：US10604994

    申请日：2003-08-29

    申请人： Toshiaki Kirihata ,  Hoki Kim ,  Matthew Wordeman

    发明人： Toshiaki Kirihata ,  Hoki Kim ,  Matthew Wordeman

    IPC分类号： G11C5/00 ,  G11C8/16 ,  G11C11/405 ,  G11C11/4099

    CPC分类号： G11C11/405 ,  G11C8/16 ,  G11C11/4099

    摘要： A multi-port memory architecture utilizing an open bitline configuration for the read bitline is described. The memory is sub-divided into two arrays (A and B) consisting of memory gain cells arranged in a matrix formation, the cells having two general ports or separate read and write ports to enable simultaneous a read and write operation. Each memory array includes a reference wordline coupled to reference cells. When the reference cell is accessed, the read bitline (RBL) discharges to a level at half the value taken by a cell storing a 0 or 1. Each pair of RBLB in the same column of the two arrays is coupled to a differential sense amplifier, and each write bitline (WBL) in the two arrays is linked to write drivers WBLs in the two arrays are driven to the same voltage and at the same slew rate. The WBL swing in each array creates coupling noise by the bitline-to-bitline capacitors. For a given sense amplifier and its associated RBLs, the coupling creates an identical coupling noise on RBLA and RBLB that are positioned in the two arrays A and B. This common mode noise is rejected by the differential sense amplifier. Thus, a read sense amplifier can accurately discriminate between the signal by activating the cell by way of RWL, and the reference cell by way of REFWL.

    摘要翻译： 描述了利用读取位线的开放位线配置的多端口存储器架构。 存储器被细分为由矩阵形式排列的存储器增益单元组成的两个阵列（A和B），这些单元具有两个通用端口或单独的读取和写入端口，以实现读写操作。 每个存储器阵列包括耦合到参考单元的参考字线。 当参考单元被访问时，读位线（RBL）放电到由存储0或1的单元取得的值的一半的电平上。两个阵列的同一列中的每对RBLB耦合到差分读出放大器 ，并且两个阵列中的每个写入位线（WBL）链接到写入驱动器，两个阵列中的WBLs被驱动到相同的电压和相同的转换速率。 每个阵列中的WBL摆幅通过位线到位线电容产生耦合噪声。 对于给定的读出放大器及其相关联的RBL，耦合在位于两个阵列A和B中的RBLA和RBLB上产生相同的耦合噪声。这种共模噪声被差分读出放大器拒绝。 因此，读出读出放大器可以通过RWL通过激活单元以及通过REFWL来使参考单元精确地区分信号。

    GAIN CELL MEMORY HAVING READ CYCLE INTERLOCK
    8.
    发明申请
    GAIN CELL MEMORY HAVING READ CYCLE INTERLOCK 有权
    具有读取周期互锁的增益单元存储器

    公开(公告)号：US20050024923A1

    公开(公告)日：2005-02-03

    申请号：US10604374

    申请日：2003-07-15

    申请人： Hoki Kim ,  Toshiaki Kirihata

    发明人： Hoki Kim ,  Toshiaki Kirihata

    IPC分类号： G11C7/00 ,  G11C7/22 ,  G11C8/00 ,  G11C11/24 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091

    CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/4085 ,  G11C11/409 ,  G11C11/4091 ,  G11C2207/2281

    摘要： A method is provided for accessing a storage cell of a dynamic random access memory (DRAM) having an array of gain cells being read accessible by a read wordline and a read bitline, and being write accessible by a write wordline and write bitline separate from said read wordline and read bitline. The method includes activating a read wordline of the array of gain cells to permit signals from a plurality of gain cells coupled to the read wordline to develop on a plurality of corresponding read bitlines coupled to the gain cells. An interlock signal is then generated in the DRAM after activating the read wordline. The read wordline is then deactivated in response to the interlock signal.

    摘要翻译： 提供一种用于访问动态随机存取存储器（DRAM）的存储单元的方法，该存储单元具有读取字线和读取位线可读取的增益单元阵列，并且可由写入字线写入和与所述读取字线分开的写入位线 阅读字线并阅读位线。 该方法包括激活增益单元阵列的读取字线以允许耦合到读取字线的多个增益单元的信号在耦合到增益单元的多个对应读取位线上形成。 然后在激活读取字线之后，在DRAM中产生互锁信号。 然后，读取的字线响应于互锁信号被去激活。

    Three dimensional twisted bitline architecture for multi-port memory
    9.
    发明授权
    Three dimensional twisted bitline architecture for multi-port memory 失效
    用于多端口存储器的三维扭转位线架构

    公开(公告)号：US07885138B2

    公开(公告)日：2011-02-08

    申请号：US11875173

    申请日：2007-10-19

    申请人： Hoki Kim ,  Toshiaki Kirihata

    发明人： Hoki Kim ,  Toshiaki Kirihata

    IPC分类号： G11C8/00

    CPC分类号： G11C8/16 ,  G11C7/02 ,  G11C7/1075 ,  G11C7/18 ,  G11C11/412

    摘要： Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.

    摘要翻译： 本发明的实施例提供了双重部分单元的存储器阵列及其设计结构。 存储器阵列具有一对扭曲的写位线和用于每列的一对扭转的读位线。 通过在列的每个部分中交替每个位线对的垂直位置来进行扭转，从而产生共模鼻子并且减小差模噪声。

    Dynamic random access memory with smart refresh scheduler
    10.
    发明授权
    Dynamic random access memory with smart refresh scheduler 有权
    具有智能刷新调度器的动态随机存取存储器

    公开(公告)号：US06954387B2

    公开(公告)日：2005-10-11

    申请号：US10604375

    申请日：2003-07-15

    申请人： Hoki Kim ,  Toshiaki Kirihata ,  David R. Hanson ,  Gregory J. Fredeman ,  John Golz

    发明人： Hoki Kim ,  Toshiaki Kirihata ,  David R. Hanson ,  Gregory J. Fredeman ,  John Golz

    IPC分类号： G11C11/406 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C2207/104

    摘要： In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.

    摘要翻译： 在包括多个存储体的DRAM中，对于每个存储体，存在分别向上/向下移位的标志位寄存器的一对分离的标志位寄存器。 每个组的比较器提供一个比较器输出。 每个存储体的仲裁器被连接以从该存储体的标志位寄存器和对于该存储体的比较器输出的比较器输出标志位向上信号和标志位降低信号。 仲裁器被连接以接收信号中的冲突并提供冲突信号。 一对标志位寄存器表示每个存储体的刷新状态，并指定准备进行刷新操作的存储体或阵列。