- 专利标题: Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design
-
申请号: US10947498申请日: 2004-09-22
-
公开(公告)号: US07149989B2公开(公告)日: 2006-12-12
- 发明人: Viswanathan Lakshmanan , Alan Holesovsky , Lisa M. Miller , Jonathan P. Kuppinger
- 申请人: Viswanathan Lakshmanan , Alan Holesovsky , Lisa M. Miller , Jonathan P. Kuppinger
- 申请人地址: US CA Milpitas
- 专利权人: LSI Logic Corporation
- 当前专利权人: LSI Logic Corporation
- 当前专利权人地址: US CA Milpitas
- 代理商 Eric James Whitesell
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A method and computer program product for early physical design validation and identification of texted metal short circuits in an integrated circuit design includes steps of: (a) receiving as input a representation of an integrated circuit design; (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to one of identifying texted metal short circuits in the integrated circuit design and power distribution and input/output cell placement in the integrated circuit design; and (d) performing a physical design validation on the integrated circuit design from the specific rule deck.
公开/授权文献
信息查询