Invention Grant
- Patent Title: Conductive bumps with non-conductive juxtaposed sidewalls
- Patent Title (中): 具有非导电并置侧壁的导电凸块
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Application No.: US10714277Application Date: 2003-11-14
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Publication No.: US07154176B2Publication Date: 2006-12-26
- Inventor: Yuan-Chang Huang , Shyh-Ming Chang , Su-Chia Lu
- Applicant: Yuan-Chang Huang , Shyh-Ming Chang , Su-Chia Lu
- Applicant Address: TW Hsinchu
- Assignee: Industrial Technology Research Institute
- Current Assignee: Industrial Technology Research Institute
- Current Assignee Address: TW Hsinchu
- Agency: Akin Gump Strauss Hauer & Feld, LLP
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L23/48

Abstract:
A microelectronic structure having a substrate of multiple conductive bumps for contact with bond pads on an electronic substrate in the fabrication of a flip chip electronic assembly. Each of the conductive bumps includes a conductive layer which is absent from at least one sidewall of the bump to prevent the inadvertent formation of a short-circuiting electrical path between adjacent conductive bumps in the electronic assembly.
Public/Granted literature
- US20050104223A1 Conductive bumps with non-conductive juxtaposed sidewalls and method for fabricating Public/Granted day:2005-05-19
Information query
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