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65 条记录 (耗时 0.021 秒)

    Method for forming self-cleaning coating comprising hydrophobically-modified particles
    1.
    发明授权
    Method for forming self-cleaning coating comprising hydrophobically-modified particles 有权
    用于形成包含疏水改性颗粒的自清洁涂层的方法

    公开(公告)号：US07744953B2

    公开(公告)日：2010-06-29

    申请号：US11318566

    申请日：2005-12-28

    申请人： Yuan-Chang Huang ,  Yuung-Ching Sheen ,  Yih-Her Chang ,  Kuo-Feng Lo

    发明人： Yuan-Chang Huang ,  Yuung-Ching Sheen ,  Yih-Her Chang ,  Kuo-Feng Lo

    IPC分类号： B05D3/02

    CPC分类号： B05D5/08 ,  Y10T428/2809

    摘要： A method for forming self-cleaning coating comprising hydrophobically-modified particles. Micro- or nano-particles are treated with a hydrophobic agent and an additive to form larger particles with the hydrophobic agent and the additive bonded thereto. A binder or crosslinker is attached to the larger particles by forming chemical bonds with at least one of the additive, the hydrophobic agent, and the particles, thus forming a coating material capable of forming self-cleaning coating.

    摘要翻译： 一种形成包含疏水改性颗粒的自清洁涂层的方法。 用疏水剂和添加剂处理微米或纳米颗粒以与疏水剂和添加剂结合的较大颗粒形成。 通过与添加剂，疏水剂和颗粒中的至少一种形成化学键，粘合剂或交联剂附着到较大的颗粒上，从而形成能够形成自清洁涂层的涂料。

    Wafer level package structure of optical-electronic device and method for making the same
    4.
    发明授权
    Wafer level package structure of optical-electronic device and method for making the same 失效
    光电子器件的晶圆级封装结构及其制造方法

    公开(公告)号：US07317235B2

    公开(公告)日：2008-01-08

    申请号：US11082899

    申请日：2005-03-18

    申请人： Yuan-Chang Huang ,  Tai-Hung Chen ,  Yao-Sheng Lin ,  Su-Tsai Lu

    发明人： Yuan-Chang Huang ,  Tai-Hung Chen ,  Yao-Sheng Lin ,  Su-Tsai Lu

    IPC分类号： H01L31/0203

    CPC分类号： H01L27/14683 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

    摘要： A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.

    摘要翻译： 公开了一种光电子器件的晶片级封装结构及其制造方法。 光电子器件的晶片级封装结构通过采用其表面具有多个光敏区域并分成单个封装器件的衬底来提供。 制造步骤首先涉及提供具有表面具有光敏区域和接合焊盘的几个芯片的基板，并且提供其表面具有导电电路和划线的透明层。 然后，接合焊盘接合到导电电路，并且在芯片上形成保护层以暴露部分导电电路。 在保护层上形成导电膜，并且导电膜与延伸的导电电路接触以形成光电子器件的晶片级封装结构。 最后，根据划线对透明层进行切割，形成单独的封装装置。

    Use of a novel capped anneal procedure to improve salicide formation
    7.
    发明授权
    Use of a novel capped anneal procedure to improve salicide formation 有权
    使用新型封端退火方法来改善自杀化合物的形成

    公开(公告)号：US06211083B1

    公开(公告)日：2001-04-03

    申请号：US09550263

    申请日：2000-04-17

    申请人： Jiunn-Der Yang ,  Chaucer Chung ,  Yuan-Chang Huang

    发明人： Jiunn-Der Yang ,  Chaucer Chung ,  Yuan-Chang Huang

    IPC分类号： H01L214763

    CPC分类号： H01L29/665 ,  H01L21/28518

    摘要： A process for forming a low resistance, titanium disilicide layer, on regions of a MOSFET device, has been developed. The process features the deposition of a capping, silicon oxide layer, on first phase, high resistance, titanium disilicide regions. The capping, silicon oxide layer, featuring a compressive stress, reduces the risk of titanium disilicide regions, formed with a tensile stress, from adhesion loss, or peeling, from underlying regions of the MOSFET device, such as from the top surface of a narrow width, polysilicon gate structure. In addition the capping silicon oxide layer protects underlying titanium disilicide regions from the ambient used during the anneal cycle used to convert the first phase, high resistance, titanium disilicide region, to the second phase, low resistance, titanium disilicide region.

    摘要翻译： 已经开发了在MOSFET器件的区域上形成低电阻二硅化钛层的工艺。 该方法的特征在于在第一相，高电阻，二硅化钛区域上沉积封盖的氧化硅层。 封装，氧化硅层具有压缩应力，降低了形成有拉伸应力的二硅化钛区域从MOSFET器件的下面区域的粘附损失或剥离的风险，例如从狭窄的顶部表面 宽度，多晶硅栅结构。 此外，封盖氧化硅层保护下游的二硅化钛区域与用于将第一相，高电阻，二硅化钛区域转化为第二相，低电阻，二硅化钛区域的退火循环期间使用的环境。

    Method for patterning a polysilicon gate in deep submicron technology
    8.
    发明授权
    Method for patterning a polysilicon gate in deep submicron technology 有权
    在深亚微米技术中构图多晶硅栅极的方法

    公开(公告)号：US6156629A

    公开(公告)日：2000-12-05

    申请号：US164998

    申请日：1998-10-01

    申请人： Hun-Jan Tao ,  Yuan-Chang Huang

    发明人： Hun-Jan Tao ,  Yuan-Chang Huang

    IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/26

    CPC分类号： H01L21/28123 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32137 ,  Y10S438/952

    摘要： A method of etching polysilicon using an oxide hard mask using a three step etch process. Steps one and two are performed insitu in a high density plasma (e.g., TCP--transformer coupled plasma) oxide etcher. Step 3, the polysilicon etch is performed in a different etcher (e.g., poly RIE etcher). A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30.a) in STEP 1, etching the bottom anti-reflective coating (BARC) layer and the hard mask layer by flowing fluorocarbon gas species gas and argon gas, and applying a first TCP Power and a first Bias power;b) in STEP 2, stripping the bottom anti-reflective coating (BARC) layer by flowing a oxygen; and applying a second TCP Power and second Bias power;c) Placing the substrate into a polysilicon high density plasma etcher and performing the following step: in STEP 3--etching the polysilicon layer by flowing chlorine species, oxygen species; Helium species and bromine gas species and applying a third TCP Power and a third Bias power.

    摘要翻译： 使用三步蚀刻工艺使用氧化物硬掩模蚀刻多晶硅的方法。 第一步和第二步在高密度等离子体（例如，TCP-变压耦合等离子体）氧化物蚀刻器中进行。 步骤3，多晶硅蚀刻在不同的蚀刻器（例如，多RIE蚀刻器）中进行。 形成多层半导体结构35（图1），包括：基板10，栅极氧化物层14，多晶硅层18，硬掩模层22和底部抗反射涂层（BARC）层26和 抗蚀剂层30. a）在步骤1中，通过流过碳氟化合物气体种类的气体和氩气蚀刻底部抗反射涂层（BARC）层和硬掩模层，并施加第一TCP电力和第一偏压功率; b）在步骤2中，通过流动氧来汽提底部抗反射涂层（BARC）层; 以及施加第二TCP功率和第二偏置功率; c）将衬底放入多晶硅高密度等离子体蚀刻机中，并执行以下步骤：在步骤3中，通过流动氯物质，氧物种蚀刻多晶硅层; 氦物种和溴气物种，并应用第三个TCP电源和第三个偏置电源。

    Dimple-free tungsten plug
    10.
    发明授权
    Dimple-free tungsten plug 失效
    无铅钨丝塞

    公开(公告)号：US5672914A

    公开(公告)日：1997-09-30

    申请号：US635802

    申请日：1996-04-22

    申请人： Yuan-Chang Huang ,  Huang-Hui Chang

    发明人： Yuan-Chang Huang ,  Huang-Hui Chang

    IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L29/40 ,  H01L29/54 ,  H01L29/62

    CPC分类号： H01L21/76877 ,  Y10S438/976

    摘要： A new method of metallization using a dimple-free tungsten plug is described. Semiconductor device structures are formed in and on a semiconductor substrate. An insulating layer is deposited overlying the semiconductor device structures. An opening is etched through the insulating layer to contact one of the semiconductor device structures. A layer of tungsten is deposited overlying the insulating layer and within the opening. The tungsten layer is coated with a layer of spin-on-glass wherein the spin-on-glass layer planarizes the top surface of the substrate. The spin-on-glass and tungsten layers are etched back leaving the tungsten layer only within the opening as a tungsten plug wherein the presence of the spin-on-glass layer overlying the tungsten layer prevents the formation of a dimple within the tungsten plug completing the formation of the dimple-free tungsten plug in the fabrication of an integrated circuit.

    摘要翻译： 描述了使用无凹坑钨塞的金属化的新方法。 在半导体衬底中形成半导体器件结构。 绝缘层沉积在半导体器件结构上。 通过绝缘层蚀刻开口以接触半导体器件结构之一。 覆盖绝缘层和开口内的钨层被沉积。 钨层涂有一层旋涂玻璃，其中旋涂玻璃层将基材的顶表面平坦化。 将旋涂玻璃和钨层刻蚀回留留下钨层作为钨丝塞，其中覆盖钨层的旋涂玻璃层的存在防止在钨塞内完成凹坑的形成 在制造集成电路时形成无凹槽的钨插头。