Invention Grant
- Patent Title: I/O circuit placement method and semiconductor device
- Patent Title (中): I / O电路放置方法和半导体器件
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Application No.: US10733095Application Date: 2003-12-11
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Publication No.: US07165232B2Publication Date: 2007-01-16
- Inventor: Wang-Jin Chen , Chen-Teng Fan , Cheng-I Huang , Ya-Yun Liu
- Applicant: Wang-Jin Chen , Chen-Teng Fan , Cheng-I Huang , Ya-Yun Liu
- Applicant Address: TW Hsin-Chu
- Assignee: Faraday Technology Corp.
- Current Assignee: Faraday Technology Corp.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L29/40

Abstract:
An I/O circuit placement method. In the I/O circuit placement method, at least two rows of I/O circuits are placed on a first side of the chip, and each I/O circuit has a head section and a tail section. The placement direction of the head section and the tail section is perpendicular to the placement direction of the I/O circuits in the rows. The semiconductor further has a core circuit disposed on the chip, wherein the rows of I/O circuits are disposed outside the core circuit and are at the periphery of the chip. Due to the I/O circuit placement in the semiconductor device, the present invention reduces the area of the semiconductor chip and fabrication cost.
Public/Granted literature
- US20050127405A1 I/O circuit placement method and semiconductor device Public/Granted day:2005-06-16
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