公开(公告)号：US20060197518A1

公开(公告)日：2006-09-07

申请号：US11306382

申请日：2005-12-27

Applicant: Shyh-An Chi ,  Wang-Jin Chen

Inventor： Shyh-An Chi ,  Wang-Jin Chen

IPC: G01R31/28

CPC classification number: G01R31/31712

Abstract: A parametric measuring circuit for minimizing an oscillation effect is provided. The parametric measuring circuit comprises an input detection circuit, an oscillation effect eliminating logic circuit and an output selection circuit. The input detection circuit receives an input signal from an external input terminal and outputs the detection signal. The oscillation effect eliminating logic circuit is coupled to the input detection circuit for reducing/eliminating oscillation effect and outputting the detection signal. The output selection circuit is coupled to the oscillation effect eliminating logic circuit to select and transmit either the output signal generated from the internal circuit or the detection signal to the output terminal.

公开(公告)号：US20090014801A1

公开(公告)日：2009-01-15

申请号：US11775584

申请日：2007-07-10

Applicant: Wang-Jin Chen ,  Chia-Nan Hong

Inventor： Wang-Jin Chen ,  Chia-Nan Hong

IPC: H01L23/62

CPC classification number: H01L27/0266

Abstract: In order to reduce the leakage current and increase the ESD protection performance, several MOS capacitors are serially connected. The E field between the gate and the source/drain of the MOS transistor is lowered and so is the gate leakage current. Besides, because the ESD voltage is distributed on the gates of the MOS capacitors, the MOS capacitors have good ESD protection performance.

Abstract translation: 为了降低漏电流并增加ESD保护性能，几个MOS电容串联。 MOS晶体管的栅极和源极/漏极之间的E场降低，栅极漏电流也降低。 此外，由于ESD电压分布在MOS电容器的栅极上，所以MOS电容器具有良好的ESD保护性能。

公开(公告)号：US07394272B2

公开(公告)日：2008-07-01

申请号：US11306773

申请日：2006-01-11

Applicant: Wang-Jin Chen ,  Aviles Chang

Inventor： Wang-Jin Chen ,  Aviles Chang

IPC: G01R31/02

CPC classification number: G01R31/31855 ,  G11C5/04 ,  G11C29/36 ,  G11C2029/0405 ,  G11C2029/3602

Abstract: A SIP (system in package) with a chip and a memory mode, capable of performing integration test on the memory module even if the memory module does not include any scan chain is provided. The chip has a built-in self-test (BIST) circuit, which generates test pattern signals to test the memory module in response to a mode signal. Under a test mode, after the memory module receives the test pattern signals, the memory module outputs responsive readout signals to the BIST circuit and the BIST circuit determines and outputs a test result and a test record in response to the readout signals. If the test fails, conditions of the faulty memory module are recognized from the test record.

Abstract translation: 提供具有芯片和存储器模式的SIP（包括系统），能够对存储器模块执行集成测试，即使存储器模块不包括任何扫描链。 该芯片具有内置自检（BIST）电路，可生成测试模式信号，以响应模式信号测试存储器模块。 在测试模式下，在存储器模块接收测试模式信号之后，存储器模块向BIST电路输出响应读出信号，并且BIST电路响应于读出信号确定并输出测试结果和测试记录。 如果测试失败，则从测试记录中识别故障存储器模块的状况。

公开(公告)号：US20070159201A1

公开(公告)日：2007-07-12

申请号：US11306773

申请日：2006-01-11

Applicant: Wang-Jin Chen ,  Aviles Chang

Inventor： Wang-Jin Chen ,  Aviles Chang

IPC: G01R31/26

CPC classification number: G01R31/31855 ,  G11C5/04 ,  G11C29/36 ,  G11C2029/0405 ,  G11C2029/3602

Abstract: A SIP (system in package) with a chip and a memory mode, capable of performing integration test on the memory module even if the memory module does not include any scan chain is provided. The chip has a built-in self-test (BIST) circuit, which generates test pattern signals to test the memory module in response to a mode signal. Under a test mode, after the memory module receives the test pattern signals, the memory module outputs responsive readout signals to the BIST circuit and the BIST circuit determines and outputs a test result and a test record in response to the readout signals. If the test fails, conditions of the faulty memory module are recognized from the test record.

Abstract translation: 提供具有芯片和存储器模式的SIP（包括系统），能够对存储器模块执行集成测试，即使存储器模块不包括任何扫描链。 该芯片具有内置自检（BIST）电路，可生成测试模式信号，以响应模式信号测试存储器模块。 在测试模式下，在存储器模块接收测试模式信号之后，存储器模块向BIST电路输出响应读出信号，并且BIST电路响应于读出信号确定并输出测试结果和测试记录。 如果测试失败，则从测试记录中识别故障存储器模块的状况。

公开(公告)号：US07165232B2

公开(公告)日：2007-01-16

申请号：US10733095

申请日：2003-12-11

Applicant: Wang-Jin Chen ,  Chen-Teng Fan ,  Cheng-I Huang ,  Ya-Yun Liu

Inventor： Wang-Jin Chen ,  Chen-Teng Fan ,  Cheng-I Huang ,  Ya-Yun Liu

IPC: G06F17/50 ,  H01L29/40

CPC classification number: H01L27/11898 ,  H01L27/0207

Abstract: An I/O circuit placement method. In the I/O circuit placement method, at least two rows of I/O circuits are placed on a first side of the chip, and each I/O circuit has a head section and a tail section. The placement direction of the head section and the tail section is perpendicular to the placement direction of the I/O circuits in the rows. The semiconductor further has a core circuit disposed on the chip, wherein the rows of I/O circuits are disposed outside the core circuit and are at the periphery of the chip. Due to the I/O circuit placement in the semiconductor device, the present invention reduces the area of the semiconductor chip and fabrication cost.

Abstract translation: 一种I / O电路放置方法。 在I / O电路放置方法中，至少两行I / O电路放置在芯片的第一侧上，并且每个I / O电路具有头部和尾部。 头部和尾部的放置方向垂直于行中的I / O电路的放置方向。 半导体还具有设置在芯片上的核心电路，其中I / O电路行设置在核心电路的外部并且位于芯片的外围。 由于半导体器件中的I / O电路布置，本发明减小了半导体芯片的面积和制造成本。

公开(公告)号：US06978411B2

公开(公告)日：2005-12-20

申请号：US10265700

申请日：2002-10-08

Applicant: Cheng-I Huang ,  Chen-Teng Fan ,  Wang-Jin Chen ,  Jyh-Herny Wang

Inventor： Cheng-I Huang ,  Chen-Teng Fan ,  Wang-Jin Chen ,  Jyh-Herny Wang

IPC: G11C29/56 ,  G01R31/28

CPC classification number: G11C29/56012 ,  G11C29/56

Abstract: A memory test system for peak power reduction. The memory test system includes a plurality of memories, a plurality of memory built-in self-test circuits and a plurality of delay units. Each of the memory built-in self-test circuits comprises a built-in self-test controller for receiving a clock signal and producing a plurality of required control signals to test one of the memories. Each of the delay units is coupled between two adjacent built-in self-test controllers. The clock signal input to one of the built-in self-test controllers is received by the delay unit to produce a delayed clock signal, and the delay unit outputs the delayed clock signal to the other.

Abstract translation: 用于峰值功率降低的记忆测试系统。 存储器测试系统包括多个存储器，多个存储器内置自检电路和多个延迟单元。 每个存储器内置的自检电路包括内置的自检控制器，用于接收时钟信号并产生多个所需的控制信号以测试其中一个存储器。 每个延迟单元耦合在两个相邻的内置自检控制器之间。 输入到内置自检控制器之一的时钟信号由延迟单元接收以产生延迟的时钟信号，并且延迟单元将延迟的时钟信号输出到另一个。

公开(公告)号：US20050127405A1

公开(公告)日：2005-06-16

申请号：US10733095

申请日：2003-12-11

Applicant: Wang-Jin Chen ,  Chen-Teng Fan ,  Cheng-I Huang ,  Ya-Yun Liu

Inventor： Wang-Jin Chen ,  Chen-Teng Fan ,  Cheng-I Huang ,  Ya-Yun Liu

IPC: G06F9/45 ,  H01L23/48 ,  H01L23/52 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L27/11898 ,  H01L27/0207

Abstract: An I/O circuit placement method. In the I/O circuit placement method, at least two rows of I/O circuits are placed on a first side of the chip, and each I/O circuit has a head section and a tail section. The placement direction of the head section and the tail section is perpendicular to the placement direction of the I/O circuits in the rows. The semiconductor further has a core circuit disposed on the chip, wherein the rows of I/O circuits are disposed outside the core circuit and are at the periphery of the chip. Due to the I/O circuit placement in the semiconductor device, the present invention reduces the area of the semiconductor chip and fabrication cost.

Abstract translation: 一种I / O电路放置方法。 在I / O电路放置方法中，至少两行I / O电路放置在芯片的第一侧上，并且每个I / O电路具有头部和尾部。 头部和尾部的放置方向垂直于行中的I / O电路的放置方向。 半导体还具有设置在芯片上的核心电路，其中I / O电路行设置在核心电路的外部并且位于芯片的外围。 由于半导体器件中的I / O电路布置，本发明减小了半导体芯片的面积和制造成本。

公开(公告)号：US06895540B2

公开(公告)日：2005-05-17

申请号：US10064475

申请日：2002-07-18

Applicant: Wang-Jin Chen ,  Chen-Teng Fan ,  Cheng-I Huang

Inventor： Wang-Jin Chen ,  Chen-Teng Fan ,  Cheng-I Huang

IPC: G01R31/3185 ,  G01R31/28 ,  G06F9/45 ,  H01L25/00

CPC classification number: G01R31/318594 ,  G01R31/318541

Abstract: A mux scan cell includes a multiplexer having a first input node for receiving raw data, a second input node for receiving test data, an output node, a selection node, and a delay circuit electrically connected between the second input node and the output node for prolonging a traveling time which the test data takes to travel from the second input node to the output node. The mux scan cell also includes a flip-flop connected to the multiplexer. With the delay circuit, the traveling time of the test data is prolonged such that the traveling time which the test data takes to travel from the second input node to the output node simulates a sum of a traveling time in which the raw data travels through a combinational logic and a traveling time in which the raw data travels from the first input node to the output node.

Abstract translation: 多路复用扫描单元包括多路复用器，其具有用于接收原始数据的第一输入节点，用于接收测试数据的第二输入节点，输出节点，选择节点和电连接在第二输入节点和输出节点之间的延迟电路，用于 延长测试数据从第二输入节点到输出节点行进的行进时间。 复用器扫描单元还包括连接到多路复用器的触发器。 利用延迟电路，延长测试数据的行进时间，使得测试数据从第二输入节点行进到输出节点的行进时间模拟原始数据行进通过的行进时间的总和 组合逻辑和原始数据从第一输入节点传播到输出节点的行进时间。