发明授权
US07167056B2 High performance analog charge pumped phase locked loop (PLL) architecture with process and temperature compensation in closed loop bandwidth
有权
高性能模拟电荷泵浦锁相环（PLL）架构，在闭环带宽中具有过程和温度补偿
- 专利标题： High performance analog charge pumped phase locked loop (PLL) architecture with process and temperature compensation in closed loop bandwidth
- 专利标题（中）： 高性能模拟电荷泵浦锁相环（PLL）架构，在闭环带宽中具有过程和温度补偿
-
申请号： US10955064申请日： 2004-09-30
-
公开(公告)号： US07167056B2公开(公告)日： 2007-01-23
- 发明人: Lieyi Fang , Asit Shankar , Lars Risbo
- 申请人： Lieyi Fang , Asit Shankar , Lars Risbo
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Alan K. Stewart; W. James Brady; Frederick J. Telecky, Jr.
- 主分类号： H03K3/03
- IPC分类号： H03K3/03 ; H03B5/12 ; H03L7/093
摘要：
The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)(10) with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product KVCO*ICP independent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump (16).
公开/授权文献
信息查询
IPC分类:
