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1.发明授权High performance analog charge pumped phase locked loop (PLL) architecture with process and temperature compensation in closed loop bandwidth 有权高性能模拟电荷泵浦锁相环（PLL）架构，在闭环带宽中具有过程和温度补偿公开(公告)号：US07167056B2
公开(公告)日：2007-01-23
申请号：US10955064
申请日：2004-09-30
申请人： Lieyi Fang , Asit Shankar , Lars Risbo
发明人： Lieyi Fang , Asit Shankar , Lars Risbo
CPC分类号： H03L7/0995 , H03L7/0891 , H03L2207/04
摘要： The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)(10) with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product KVCO*ICP independent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump (16).
摘要翻译： 本发明实现了在闭环带宽中具有过程和温度补偿的高性能模拟电荷泵浦锁相环（PLL）（10）的技术优点。 PLL通过不依赖于过程和温度变化产生产品K VCO，从而减小带宽和稳定性的变化。 PLL实现了比现有PLL架构更高的性能，实现高达至少110 dB的高动态范围，从而可以利用该PLL实现PWM D类放大器。 使用模拟电荷泵（16）时，PLL具有恒定的带宽和阻尼因子。
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2.发明申请High performance analog charge pumped phase locked loop (PLL) architecture with process and temperature compensation in closed loop bandwidth 有权高性能模拟电荷泵浦锁相环（PLL）架构，在闭环带宽中具有过程和温度补偿公开(公告)号：US20060071716A1
公开(公告)日：2006-04-06
申请号：US10955064
申请日：2004-09-30
申请人： Lieyi Fang , Asit Shankar , Lars Risbo
发明人： Lieyi Fang , Asit Shankar , Lars Risbo
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03L7/0891 , H03L2207/04
摘要： The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)(10) with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product KVCO*ICP independent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump (16).
摘要翻译： 本发明实现了在闭环带宽中具有过程和温度补偿的高性能模拟电荷泵浦锁相环（PLL）（10）的技术优点。 PLL通过不依赖于过程和温度变化产生产品K VCO，从而减小带宽和稳定性的变化。 PLL实现了比现有PLL架构更高的性能，实现高达至少110 dB的高动态范围，从而可以利用该PLL实现PWM D类放大器。 使用模拟电荷泵（16）时，PLL具有恒定的带宽和阻尼因子。
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公开(公告)号：US07425874B2
公开(公告)日：2008-09-16
申请号：US11427853
申请日：2006-06-30
IPC分类号： H03L7/093
CPC分类号： H03L7/093 , H03L7/089 , H03L7/0991 , H03L7/0995
摘要： A digital audio system including a digital phase-locked-loop circuit for generating a pulse-width-modulation (PWM) clock signal, applied to a pulse-code-modulation to pulse-width-modulation converter, is disclosed. The digital phase-locked loop includes a phase detector for measuring phase error between a reference signal and a feedback signal. A digital version of the phase error, after filtering by a loop filter, is converted to a digital delay control word that is sampled at twice its frequency. Successive samples of the delay control word control the propagation delay of first and second delay cells in an oscillator. The use of successive samples at substantially twice the frequency of change of the delay control word effectively realizes the sum of a sinc filter and a comb filter, which greatly suppresses the effects of jitter in the reference signal to the digital phase-locked loop.
摘要翻译： 公开了一种数字音频系统，包括用于产生施加到脉冲编码调制脉宽调制转换器的脉冲宽度调制（PWM）时钟信号的数字锁相环电路。 数字锁相环包括用于测量参考信号和反馈信号之间的相位误差的相位检测器。 在通过环路滤波器滤波之后，相位误差的数字版本被转换成以两倍的频率被采样的数字延迟控制字。 延迟控制字的连续样本控制振荡器中第一和第二延迟单元的传播延迟。 以延迟控制字的变化频率基本上两倍的连续样本的使用有效地实现了sinc滤波器和梳状滤波器的总和，其大大抑制了参考信号中的抖动对数字锁相环的影响。
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公开(公告)号：US20080012647A1
公开(公告)日：2008-01-17
申请号：US11427853
申请日：2006-06-30
IPC分类号： H03L7/00
CPC分类号： H03L7/093 , H03L7/089 , H03L7/0991 , H03L7/0995
摘要： A digital audio system including a digital phase-locked-loop circuit for generating a pulse-width-modulation (PWM) clock signal, applied to a pulse-code-modulation to pulse-width-modulation converter, is disclosed. The digital phase-locked loop includes a phase detector for measuring phase error between a reference signal and a feedback signal. A digital version of the phase error, after filtering by a loop filter, is converted to a digital delay control word that is sampled at twice its frequency. Successive samples of the delay control word control the propagation delay of first and second delay cells in an oscillator. The use of successive samples at substantially twice the frequency of change of the delay control word effectively realizes the sum of a sinc filter and a comb filter, which greatly suppresses the effects of jitter in the reference signal to the digital phase-locked loop.
摘要翻译： 公开了一种数字音频系统，包括用于产生施加到脉冲编码调制脉宽调制转换器的脉冲宽度调制（PWM）时钟信号的数字锁相环电路。 数字锁相环包括用于测量参考信号和反馈信号之间的相位误差的相位检测器。 在通过环路滤波器滤波之后，相位误差的数字版本被转换成以两倍的频率被采样的数字延迟控制字。 延迟控制字的连续样本控制振荡器中第一和第二延迟单元的传播延迟。 以延迟控制字的变化频率基本上两倍的连续样本的使用有效地实现了sinc滤波器和梳状滤波器的总和，其大大抑制了参考信号中的抖动对数字锁相环的影响。
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5.发明授权Method and system for transitioning between operation states in an output system 有权在输出系统中在运行状态之间转换的方法和系统公开(公告)号：US07554390B1
公开(公告)日：2009-06-30
申请号：US11961144
申请日：2007-12-20
申请人： Asit Shankar , Klaus Krogsgaard
发明人： Asit Shankar , Klaus Krogsgaard
IPC分类号： H03F3/38
摘要： A closed loop amplifier system comprising a modulator that provides a pulse-width modulated (PWM) output signal based on an input signal, the modulator having a variable closed loop transfer function. The system also comprises a ramp generator that provides a ramp signal to the modulator, the variable closed loop transfer function of the modulator varying as a function of the ramp signal. The system further comprises a controller that controls the ramp generator to provide the ramp signal to adjust the variable closed loop transfer function during transitions between operating states of the amplifier system.
摘要翻译： 一种闭环放大器系统，包括基于输入信号提供脉宽调制（PWM）输出信号的调制器，所述调制器具有可变闭环传递函数。 该系统还包括斜坡发生器，该斜坡发生器向调制器提供斜坡信号，调制器的可变闭环传递函数作为斜坡信号的函数而变化。 该系统还包括控制器，其控制斜坡发生器以在放大器系统的操作状态之间的转换期间提供斜坡信号来调节可变闭环传递函数。
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6.发明申请METHOD AND SYSTEM FOR TRANSITIONING BETWEEN OPERATION STATES IN AN OUTPUT SYSTEM 有权用于在输出系统中操作状态之间进行转换的方法和系统公开(公告)号：US20090160547A1
公开(公告)日：2009-06-25
申请号：US11961144
申请日：2007-12-20
申请人： Asit Shankar , Klaus Krogsgaard
发明人： Asit Shankar , Klaus Krogsgaard
摘要： A closed loop amplifier system comprising a modulator that provides a pulse-width modulated (PWM) output signal based on an input signal, the modulator having a variable closed loop transfer function. The system also comprises a ramp generator that provides a ramp signal to the modulator, the variable closed loop transfer function of the modulator varying as a function of the ramp signal. The system further comprises a controller that controls the ramp generator to provide the ramp signal to adjust the variable closed loop transfer function during transitions between operating states of the amplifier system.
摘要翻译： 一种闭环放大器系统，包括基于输入信号提供脉宽调制（PWM）输出信号的调制器，所述调制器具有可变闭环传递函数。 该系统还包括斜坡发生器，该斜坡发生器向调制器提供斜坡信号，调制器的可变闭环传递函数作为斜坡信号的函数而变化。 该系统还包括控制器，其控制斜坡发生器以在放大器系统的操作状态之间的转换期间提供斜坡信号来调节可变闭环传递函数。
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