发明授权
US07167534B2 Oversampling clock recovery circuit applicable not only to high rate data but also to low rate data
失效
过采样时钟恢复电路不仅适用于高速率数据，而且适用于低速率数据
- 专利标题： Oversampling clock recovery circuit applicable not only to high rate data but also to low rate data
- 专利标题（中）： 过采样时钟恢复电路不仅适用于高速率数据，而且适用于低速率数据
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申请号： US10100871申请日： 2002-03-19
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公开(公告)号： US07167534B2公开(公告)日： 2007-01-23
- 发明人: Satoshi Nakamura
- 申请人： Satoshi Nakamura
- 申请人地址： JP Kanagawa
- 专利权人： NEC Electronics Corporation
- 当前专利权人： NEC Electronics Corporation
- 当前专利权人地址： JP Kanagawa
- 代理机构： Scully, Scott, Murphy & Presser, P.C.
- 优先权： JP2001-079167 20010319; JP2001-396458 20011227
- 主分类号： H04L7/02
- IPC分类号： H04L7/02 ; H03K19/23 ; H03L7/06
摘要：
In an oversampling clock recovery circuit comprising first through fourth phase comparators (PD1 to PD4) and a majority circuit (10), DOWN signal output terminals (DN2(out), DN3(out)) of the second and the third phase comparators are connected to UP signal input terminals (UP3(in), UP4(in)) of the majority circuit and UP signal output terminals (UP3(out), UP4(out)) of the third and the fourth phase comparators are connected to DONW signal input terminals (DN2(in), DN3(in)) of the majority circuit.
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