A delay circuit comprising a delay line to delay an input signal that has a plurality of delay cells connected in series; a PLL circuit that supplies the delay line with a delay control voltage to control the delay; and a first selector that selects one of output signals of the delay cells.Each of the delay cells comprises two stages of delay inverters connected in series and an output inverter connected to a connection point of the delay inverter of the first stage and the delay inverter of the second stage. Input into the delay inverter of the first stage is an output signal of the delay inverter of the second stage in the preceding delay cell, and the first selector outputs as a delayed signal an output signal of the output inverter or the delay inverter of the second stage in one of the delay cells.