Invention Grant
US07176051B2 Method of reducing charging damage to integrated circuits during semiconductor manufacturing
有权
在半导体制造过程中减少集成电路的充电损坏的方法
- Patent Title: Method of reducing charging damage to integrated circuits during semiconductor manufacturing
- Patent Title (中): 在半导体制造过程中减少集成电路的充电损坏的方法
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Application No.: US10908815Application Date: 2005-05-27
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Publication No.: US07176051B2Publication Date: 2007-02-13
- Inventor: Ko-Ting Chen , Wen-Bin Lu , Chao-Hu Liang
- Applicant: Ko-Ting Chen , Wen-Bin Lu , Chao-Hu Liang
- Applicant Address: TW Hsin-Chu
- Assignee: United Microelectronics Corp.
- Current Assignee: United Microelectronics Corp.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/76

Abstract:
A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.
Public/Granted literature
- US20060270161A1 METHOD OF REDUCING CHARGING DAMAGE TO INTEGRATED CIRCUITS DURING SEMICONDUCTOR MANUFACTURING Public/Granted day:2006-11-30
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