公开(公告)号：US07157346B2

公开(公告)日：2007-01-02

申请号：US11160630

申请日：2005-07-01

Applicant: Ko-Ting Chen ,  Wen-Bin Lu ,  Chao-Hu Liang

Inventor： Ko-Ting Chen ,  Wen-Bin Lu ,  Chao-Hu Liang

IPC: H01L29/331 ,  H01L29/76

CPC classification number: H01L21/266 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/0207

Abstract: An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semiconductor substrate. Dopant species are implanted into the exposed semiconductor substrate within the first device region to form first doping regions therein. A second implant mask is formed over the semiconductor substrate. The second implant mask covers the first device region, while exposing the second device region and a portion of the non-active region. Dopant species are implanted into the exposed semiconductor substrate within the second device region to form second doping regions therein.

Abstract translation: 集成电路管芯包括第一器件区域，第二器件区域和非有源区域。 在半导体衬底上形成第一注入掩模，其覆盖第二器件区域和非有源区，同时暴露第一器件区域。 将掺杂物质注入到第一器件区域内的暴露的半导体衬底中，以在其中形成第一掺杂区域。 在半导体衬底上形成第二注入掩模。 第二植入掩模覆盖第一器件区域，同时暴露第二器件区域和非有源区域的一部分。 将掺杂物质注入第二器件区域内的暴露的半导体衬底中以在其中形成第二掺杂区域。

公开(公告)号：US07547584B2

公开(公告)日：2009-06-16

申请号：US11560831

申请日：2006-11-16

Applicant: Ko-Ting Chen ,  Wen-Bin Lu ,  Chao-Hu Liang

Inventor： Ko-Ting Chen ,  Wen-Bin Lu ,  Chao-Hu Liang

IPC: H01L21/44

CPC classification number: H01L21/266 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/823418 ,  H01L21/823481 ,  H01L23/522 ,  H01L27/0207 ,  H01L29/6659

Abstract: An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semiconductor substrate. Dopant species are implanted into the exposed semiconductor substrate within the first device region to form first doping regions therein. A second implant mask is formed over the semiconductor substrate. The second implant mask covers the first device region, while exposing the second device region and a portion of the non-active region. Dopant species are implanted into the exposed semiconductor substrate within the second device region to form second doping regions therein.

Abstract translation: 集成电路管芯包括第一器件区域，第二器件区域和非有源区域。 在半导体衬底上形成第一注入掩模，其覆盖第二器件区域和非有源区，同时暴露第一器件区域。 将掺杂物质注入到第一器件区域内的暴露的半导体衬底中，以在其中形成第一掺杂区域。 在半导体衬底上形成第二注入掩模。 第二植入掩模覆盖第一器件区域，同时暴露第二器件区域和非有源区域的一部分。 将掺杂物质注入第二器件区域内的暴露的半导体衬底中以在其中形成第二掺杂区域。

公开(公告)号：US07176051B2

公开(公告)日：2007-02-13

申请号：US10908815

申请日：2005-05-27

Applicant: Ko-Ting Chen ,  Wen-Bin Lu ,  Chao-Hu Liang

Inventor： Ko-Ting Chen ,  Wen-Bin Lu ,  Chao-Hu Liang

IPC: H01L21/00 ,  H01L21/76

CPC classification number: H01L21/823418 ,  H01L21/266 ,  H01L21/823481 ,  H01L27/0207

Abstract: A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.

Abstract translation: 提供具有被划线通道包围的集成电路管芯区域的半导体衬底。 在集成电路管芯区域内，在半导体衬底上形成第一沟槽隔离区域和第二沟槽隔离区域，其中第一沟槽隔离区域将第一有源器件区域与第二有源器件区域隔离，第二沟槽隔离区域 包括用于减小负载效应的多个沟槽虚拟特征。 在第一有源器件区上形成第一栅电极，在第二有源器件区上形成第二栅电极。 第一有源器件区域被掩蔽，而第二有源器件区域和沟槽虚拟特征被暴露。 然后执行离子注入工艺以将掺杂剂物质注入到第二有源器件区域中。

公开(公告)号：US20060270161A1

公开(公告)日：2006-11-30

申请号：US10908815

申请日：2005-05-27

Applicant: Ko-Ting Chen ,  Wen-Bin Lu ,  Chao-Hu Liang

Inventor： Ko-Ting Chen ,  Wen-Bin Lu ,  Chao-Hu Liang

IPC: H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/266 ,  H01L21/823481 ,  H01L27/0207

Abstract: A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.

公开(公告)号：US20060270174A1

公开(公告)日：2006-11-30

申请号：US11160630

申请日：2005-07-01

Applicant: Ko-Ting Chen ,  Wen-Bin Lu ,  Chao-Hu Liang

Inventor： Ko-Ting Chen ,  Wen-Bin Lu ,  Chao-Hu Liang

IPC: H01L21/331

CPC classification number: H01L21/266 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/0207

Abstract: An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semiconductor substrate. Dopant species are implanted into the exposed semiconductor substrate within the first device region to form first doping regions therein. A second implant mask is formed over the semiconductor substrate. The second implant mask covers the first device region, while exposing the second device region and a portion of the non-active region. Dopant species are implanted into the exposed semiconductor substrate within the second device region to form second doping regions therein.

Abstract translation: 集成电路管芯包括第一器件区域，第二器件区域和非有源区域。 在半导体衬底上形成第一注入掩模，其覆盖第二器件区域和非有源区，同时暴露第一器件区域。 将掺杂物质注入到第一器件区域内的暴露的半导体衬底中，以在其中形成第一掺杂区域。 在半导体衬底上形成第二注入掩模。 第二植入掩模覆盖第一器件区域，同时暴露第二器件区域和非有源区域的一部分。 将掺杂物质注入第二器件区域内的暴露的半导体衬底中以在其中形成第二掺杂区域。

公开(公告)号：US20070093057A1

公开(公告)日：2007-04-26

申请号：US11560831

申请日：2006-11-16

Applicant: Ko-Ting Chen ,  Wen-Bin Lu ,  Chao-Hu Liang

Inventor： Ko-Ting Chen ,  Wen-Bin Lu ,  Chao-Hu Liang

IPC: H01L21/44 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/266 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/823418 ,  H01L21/823481 ,  H01L23/522 ,  H01L27/0207 ,  H01L29/6659

Abstract: An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semiconductor substrate. Dopant species are implanted into the exposed semiconductor substrate within the first device region to form first doping regions therein. A second implant mask is formed over the semiconductor substrate. The second implant mask covers the first device region, while exposing the second device region and a portion of the non-active region. Dopant species are implanted into the exposed semiconductor substrate within the second device region to form second doping regions therein.

Abstract translation: 集成电路管芯包括第一器件区域，第二器件区域和非有源区域。 在半导体衬底上形成第一注入掩模，其覆盖第二器件区域和非有源区，同时暴露第一器件区域。 将掺杂物质注入到第一器件区域内的暴露的半导体衬底中，以在其中形成第一掺杂区域。 在半导体衬底上形成第二注入掩模。 第二植入掩模覆盖第一器件区域，同时暴露第二器件区域和非有源区域的一部分。 将掺杂物质注入第二器件区域内的暴露的半导体衬底中以在其中形成第二掺杂区域。