发明授权
- 专利标题: Vertical dual gate field effect transistor
- 专利标题(中): 垂直双栅场效应晶体管
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申请号: US10853177申请日: 2004-05-26
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公开(公告)号: US07176089B2公开(公告)日: 2007-02-13
- 发明人: Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James M. Leas , William H-L Ma , Paul A. Rabidoux
- 申请人: Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , James M. Leas , William H-L Ma , Paul A. Rabidoux
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Whitham, Curtis, Christofferson & Cook, PC
- 代理商 William D. Sabo
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.
公开/授权文献
- US20040219725A1 Vertical dual gate field effect transistor 公开/授权日:2004-11-04