公开(公告)号：US07176089B2

公开(公告)日：2007-02-13

申请号：US10853177

申请日：2004-05-26

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

IPC分类号： H01L21/336

CPC分类号： H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

摘要： A method of manufacturing provides a vertical transistor particularly suitable for high density integration and which includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

摘要翻译： 一种制造方法提供特别适用于高密度积分的垂直晶体管，其包括通过在沟槽中蚀刻或外延生长而形成的半导体柱的相对侧上的潜在独立栅极结构。 栅极结构被绝缘材料包围，绝缘材料可选择性地蚀刻到围绕晶体管的隔离材料。 通过选择性地蚀刻对绝缘材料有选择性的隔离材料，对柱的下端（例如，晶体管漏极）进行接触。 柱的上端由盖​​和可选择性蚀刻材料的侧壁覆盖，使得栅极和源极连接开口也可以通过具有良好配准公差的选择性蚀刻制成。 在平行于芯片表面的方向上的柱的尺寸由隔离区域和选择性蚀刻之间的距离限定，并且柱的高度由牺牲层的厚度限定。

公开(公告)号：US06798017B2

公开(公告)日：2004-09-28

申请号：US09944665

申请日：2001-08-31

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James M. Leas ,  William H-L Ma ,  Paul A. Rabidoux

IPC分类号： H01L2976

CPC分类号： H01L29/78642 ,  H01L21/2255 ,  H01L21/76897 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

摘要： A vertical transistor particularly suitable for high density integration includes potentially independent gate structures on opposite sides of a semiconductor pillar formed by etching or epitaxial growth in a trench. The gate structure is surrounded by insulating material which is selectively etchable to isolation material surrounding the transistor. A contact is made to the lower end of the pillar (e.g. the transistor drain) by selectively etching the isolation material selective to the insulating material. The upper end of the pillar is covered by a cap and sidewalls of selectively etchable materials so that gate and source connection openings can also be made by selective etching with good registration tolerance. A dimension of the pillar in a direction parallel to the chip surface is defined by a distance between isolation regions and selective etching and height of the pillar is defined by thickness of a sacrificial layer.

摘要翻译： 特别适用于高密度集成的垂直晶体管包括通过在沟槽中蚀刻或外延生长形成的半导体柱的相对侧上的潜在的独立栅极结构。 栅极结构被绝缘材料包围，绝缘材料可选择性地蚀刻到围绕晶体管的隔离材料。 通过选择性地蚀刻对绝缘材料有选择性的隔离材料，对柱的下端（例如，晶体管漏极）进行接触。 柱的上端由盖​​和可选择性蚀刻材料的侧壁覆盖，使得栅极和源极连接开口也可以通过具有良好配准公差的选择性蚀刻制成。 在平行于芯片表面的方向上的柱的尺寸由隔离区域和选择性蚀刻之间的距离限定，并且柱的高度由牺牲层的厚度限定。

公开(公告)号：US06506653B1

公开(公告)日：2003-01-14

申请号：US09524677

申请日：2000-03-13

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L Ma ,  Patricia M. Marmillion ,  Donald W. Rakowski

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L Ma ,  Patricia M. Marmillion ,  Donald W. Rakowski

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/665

摘要： Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.

摘要翻译： 提供了使用一次性和永久性膜通过扩散来掺杂下层的方法。 此外，提供了在植入掺杂期间使用一次性膜的方法，并且提供了用于涂覆下层材料的表面。 这些一次性膜中的一些可以由传统的非一次性膜制成并制成一次性的。 以这种方式，可以使用不蚀刻硅基材料的下层的溶剂。 优选地，进行深度注入以形成源极/漏极区域，然后执行退火步骤以激活掺杂剂。 沉积保形层并用掺杂剂注入。 执行一个或多个退火步骤以在源极/漏极区域中产生非常浅的延伸。

公开(公告)号：US06924200B2

公开(公告)日：2005-08-02

申请号：US10222035

申请日：2002-08-16

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L Ma ,  Patricia M. Marmillion ,  Donald W. Rakowski

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  William H-L Ma ,  Patricia M. Marmillion ,  Donald W. Rakowski

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/302 ,  H01L21/21

CPC分类号： H01L29/6659 ,  H01L21/2254 ,  H01L21/2255 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/665

摘要： Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.

摘要翻译： 提供了使用一次性和永久性膜通过扩散来掺杂下层的方法。 此外，提供了在植入掺杂期间使用一次性膜的方法，并且提供了用于涂覆下层材料的表面。 这些一次性膜中的一些可以由传统的非一次性膜制成并制成一次性的。 以这种方式，可以使用不蚀刻硅基材料的下层的溶剂。 优选地，进行深度注入以形成源极/漏极区域，然后执行退火步骤以激活掺杂剂。 沉积保形层并用掺杂剂注入。 执行一个或多个退火步骤以在源极/漏极区域中产生非常浅的延伸。

公开(公告)号：US06998332B2

公开(公告)日：2006-02-14

申请号：US10754073

申请日：2004-01-08

申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  William H-L Ma

发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  William H-L Ma

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/2815

摘要： Disclosed is a method that forms a conductive layer on a substrate and patterns sacrificial structures above the conductive layer. Next, the invention forms sidewall spacers adjacent the sacrificial structures using a spacer material capable of undergoing dimensional change, after which the invention removes the sacrificial structures in processing that leaves the sidewall spacers in place. The invention then protects selected ones of the sidewall spacers using a sacrificial mask and leaves the other ones of the sidewall spacers unprotected. This allows the invention to selectively expose the unprotected sidewall spacers to processing that changes the size of the unprotected sidewall spacers. This causes the unprotected sidewall spacers have a different size than protected sidewall spacers. Then, the invention removes the sacrificial mask and patterns the conductive layer using the sidewall spacers as a gate conductor mask to create differently sized gate conductors on the substrate. Following this, the invention removes the sidewall spacers and forms the source, drain, and channel regions adjacent the gate conductors.

摘要翻译： 公开了一种在基板上形成导电层并在导电层上方形成牺牲结构的方法。 接下来，本发明使用能够经历尺寸变化的间隔物材料形成邻近牺牲结构的侧壁间隔，此后本发明在将侧壁间隔物留在适当位置的情况下去除牺牲结构。 然后，本发明使用牺牲掩模保护所选择的侧壁间隔物，并且使侧壁间隔物中的其它侧壁隔离件不被保护。 这允许本发明选择性地将未受保护的侧壁间隔物暴露于改变未受保护的侧壁间隔物的尺寸的处理。 这导致未受保护的侧壁间隔件具有与受保护的侧壁间隔物不同的尺寸。 然后，本发明移除牺牲掩模，并且使用侧壁间隔物作为栅极导体掩模来图案化导电层，以在衬底上产生不同尺寸的栅极导体。 接下来，本发明移除侧壁间隔物并形成与栅极导体相邻的源极，漏极和沟道区域。

公开(公告)号：US06731315B1

公开(公告)日：2004-05-04

申请号：US09450531

申请日：1999-11-30

申请人： William A. Ma ,  Wayne M. Delia ,  William H-L Ma

发明人： William A. Ma ,  Wayne M. Delia ,  William H-L Ma

IPC分类号： G06F300

CPC分类号： G06F3/0481 ,  G06F2203/04805

摘要： A computer display system which displays an image and a magnified portion of the image. The magnified portion of the image is selected un,der control of a pointing device connected to the computer. A method is described for changing the characteristics of the magnified portion. A configuration utility which creates the magnified portion of the display includes a menu of display properties for the magnified portion. The properties are selected from the display menu, and each refresh of the area within the magnified portion of the image is refreshed with the selected properties. In a text/browser application, the background color, text color, text style and size may be selected differently than the remaining portion of the image displayed on the computer display.

摘要翻译： 一种显示图像和图像的放大部分的计算机显示系统。 图像的放大部分被选择为连接到计算机的指示设备的控制。 描述了用于改变放大部分的特性的方法。 创建显示器的放大部分的配置实用程序包括用于放大部分的显示属性的菜单。 从显示菜单中选择属性，并且用所选择的属性刷新图像的放大部分内的区域的每个刷新。 在文本/浏览器应用程序中，背景颜色，文本颜色，文本样式和大小可能与计算机显示屏上显示的图像的剩余部分不同。